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A robust multiplexer-based FPGA inspired by biological systems

JOURNAL OF SYSTEMS ARCHITECTURE 1997年第10期43卷 719-733页

作者： Tempesti, G Mange, D Stauffer, A Logic Systems Laboratory Department of Computer Science Swiss Federal Institute of Technology (EPFL) CH-1015 Lausanne Switzerland

Biological organisms are among the most robust systems known to man. Their robustness is based on a set of processes which cannot be adapted directly to the world of silicon but can provide an inspiration for the design of robust circuits. This paper introduces a multiplexer-based field programmable gate Array (FPGA) which we made capable of self-test and self-repair using an approach loosely based on biological mechanisms at the cellular level. The system is designed to provide on-line self-test and self-repair using a completely distributed system and a minimal amount of additional logic.

关键词： self-test self-repair field-programmable gate arrays reconfiguration embryonics

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Conversion Algorithms and Implementations for Koblitz Curve Cryptography

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IEEE TRANSACTIONS ON COMPUTERS 2010年第1期59卷 81-92页

作者： Brumley, Billy Bob Jarvinen, Kimmo U. Aalto Univ Dept Informat & Comp Sci Espoo 02150 Finland

In this paper, we discuss conversions between integers and tau-adic expansions and we provide efficient algorithms and hardware architectures for these conversions. The results have significance in elliptic curve cryptography using Koblitz curves, a family of elliptic curves offering faster computation than general elliptic curves. However, in order to enable these faster computations, scalars need to be reduced and represented using a special base-tau expansion. Hence, efficient conversion algorithms and implementations are necessary. Existing conversion algorithms require several complicated operations, such as multiprecision multiplications and computations with large rationals, resulting in slow and large implementations in hardware and microcontrollers with limited instruction sets. Our algorithms are designed to utilize only simple operations, such as additions and shifts, which are easily implementable on practically all platforms. We demonstrate the practicability of the new algorithms by implementing them on Altera Stratix II FPGAs. The implementations considerably improve both computation speed and required area compared to the existing solutions.

关键词： Elliptic curve cryptography Koblitz curves field-programmable gate arrays public-key cryptosystems

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A guide to migrating from microprocessor to FPGA coping with the support tool limitations

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MICROPROCESSORS AND MICROSYSTEMS 2000年第10期23卷 561-572页

作者： Bezerra, EA Gough, MP Univ Sussex Ctr Space Sci Sch Engn Brighton BN1 9QT E Sussex England Pontificia Univ Catolica Rio Grande do Sul PUC RS Informat Fac Porto Alegre RS Brazil

Microprocessors have been used as the main processing elements of embedded systems mainly because of their low cost, flexibility for system upgrade at the software level and because of the availability of efficient support tools. The configurable computing technology brought the software flexibility to the hardware level, but limitations in support tools are a barrier for software designers. Using a microcontroller based embedded system as a study case, this paper introduces workable strategies to be used by software designers to develop a complete embedded system (software + hardware parts) using a single description language, and circumventing support tool limitations. (C) 2000 Elsevier Science B.V. All rights reserved.

关键词： configurable computing VHDL field-programmable gate arrays embedded system computer architecture

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Algorithms for Multiplierless Multiple Constant Multiplication in Online Arithmetic

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2018年第11期37卷 5127-5142页

作者： Joseph, Georgina Binoy Devanathan, R. Toc H Inst Sci & Technol Dept Elect & Commun Engn Kochi Kerala India Hindustan Inst Technol & Sci Sch Elect Engn Madras Tamil Nadu India

Online arithmetic operators offer advantages of reduction in resource utilization and interconnection complexity besides providing pipelining at digit level. Multiplierless constant coefficient multiplication using the shift-and-add technique is widely used in digital signal processing applications. This paper proposes a novel bit serial adaptation of the parallel shift-and-add algorithm to online arithmetic. The proposed multipliers use right shifts instead of the traditional left shifts resulting in causal online implementations. Graph-based and hybrid algorithms are developed for the estimation of the distance of a constant from a set of constants in terms of the number of additions and for the synthesis of online multiple constant multipliers under area and online delay constraints. The computational complexity of the algorithms is determined. Results of implementation on randomly generated constant sets and FIR filter instances show substantial improvements in the number of operations required using the distance heuristic. Further, it is shown that the proposed techniques and algorithms result in significant savings in resource utilization, logic depth, and clock frequency compared to parallel and digit-serial algorithms.

关键词： Online arithmetic Digital signal processing Constant coefficient multiplication Graph-based algorithms field-programmable gate arrays

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Improved Direct Current Control for Grid-Connected Multilevel Inverters

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2021年第9期68卷 8289-8297页

作者： Hofmann, Martin Schaefer, Markus Montesinos-Miracle, Daniel Ackva, Ansgar Univ Appl Sci Wuerzburg Schweinfurt Elect Engn Dept D-97421 Schweinfurt Germany ZF Friedrichshafen AG E Mobil D-97424 Schweinfurt Germany Univ Politecn Cataluna Ctr Innovacio Tecnol Convertidors Estat & Acciona Dept Engn Elect Barcelona 08034 Spain

This article presents a sensorless voltage detection method for direct current control in grid-connected multilevel inverters. The direct current control is based on scalar hysteresis controller (SHC). The SHC is a simplified, and parametric direct current controller with the ability to work with an arbitrary level count on multilevel inverters. In combination with the sensorless voltage detection method, it is able to improve the switching behavior, and minimize the current error compared to existing direct current controllers. The proposed control concept is validated with experimental measurements using a three-, and five-level diode clamped inverter under steady-state conditions, and various grid disturbances. In comparison to the standard SHC method, it is verified that the proposed concept shows an improved switching behavior, and a reduced error current.

关键词： Inverters Switches Voltage control Current control Aerospace electronics Hysteresis Current control field-programmable gate arrays multilevel systems robust control

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Temporal logic replication for dynamically reconfigurable FPGA partitioning

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2003年第7期22卷 952-959页

作者： Mak, WK Young, EEY Univ S Florida Dept Comp Sci & Engn Tampa FL 33620 USA Chinese Univ Hong Kong Dept Comp Sci & Engn Shatin NT Peoples R China

In this paper, we propose the idea of temporal logic replication in dynamically reconfigurable field-programmable gate array partitioning to reduce the communication cost. We show that this is a very effective means to reduce the communication cost by taking,advantage of the slack logic capacity available. Given a K-stage temporal partition, the min-area min-cut replication problem is defined and we present an optimal algorithm to, solve it. We also present a How-based replication heuristic which is applicable When there is. a tight area bound that limits the amount of possible replication. In addition, we show a correct network. flow model for partitioning sequential circuits temporally and propose a new hierarchical flow-based performance-driven partitioner for computing initial partitions without replication.

关键词： dynamically reconfigurable FPGAs field-programmable gate arrays logic replication reconfigurable computing temporal partitioning

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Stream Processor for Real-Time Inverse Tone Mapping of Full-HD Images

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2015年第11期23卷 2531-2539页

作者： Licciardo, Gian Domenico D'Arienzo, Antonio Rubino, Alfredo Univ Salerno Dept Ind Engn I-84084 Salerno Italy

In this paper, an architecture design of a hardware accelerator capable to expand the dynamic range of low dynamic range images to the 32-bit high dynamic range counterpart is presented. The processor implements on-the-fly calculation of the edge-preserving bilateral filtering and luminance average, to elaborate a full-HD (1920 x 1080 pixels) image in 16.6 ms (60 frames/s) on field-programmable logic (FPL), by processing the incoming pixels in streaming order, without frame buffers. In this way, the design avoids the use of external DRAM and can be tightly coupled with acquiring devices, thus to enable the implementation of smart sensors. The processor complexity can be configured with different area/speed ratios to meet the requirements of different target platforms from FPLs to ASICs, obtaining, in both implementations, state-of-the-art performances.

关键词： Dynamic range field-programmable gate arrays image processing integrated circuits inverse tone mapping (iTM)

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Onboard Processing With Hybrid and Reconfigurable Computing on Small Satellites

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PROCEEDINGS OF THE IEEE 2018年第3期106卷 458-470页

作者： George, Alan D. Wilson, Christopher M. Univ Pittsburgh Dept Elect & Comp Engn Dept NSF Ctr Space High Performance & Resilient Comp Pittsburgh PA 15261 USA Univ Pittsburgh NSF Ctr Space High Performance & Resilient Comp Pittsburgh PA 15261 USA

Due to the increasing demands of onboard sensor and autonomous processing, one of the principal needs and challenges for future spacecraft is onboard computing. Space computers must provide high performance and reliability (which are often at odds), using limited resources (power, size, weight, and cost), in an extremely harsh environment (due to radiation, temperature, vacuum, and vibration). As spacecraft shrink in size, while assuming a growing role for science and defense missions, the challenges for space computing become particularly acute. For example, processing capabilities on CubeSats (smaller class of SmallSats) have been extremely limited to date, often featuring microcontrollers with performance and reliability barely sufficient to operate the vehicle let alone support various sensor and autonomous applications. This article surveys the challenges and opportunities of onboard computers for small satellites (SmallSats) and focuses upon new concepts, methods, and technologies that are revolutionizing their capabilities, in terms of two guiding themes: hybrid computing and reconfigurable computing. These innovations are of particular need and value to CubeSats and other SmallSats. With new technologies, such as CHREC Space Processor (CSP), we demonstrate how system designers can exploit hybrid and reconfigurable computing on SmallSats to harness these advantages for a variety of purposes, and we highlight several recent missions by NASA and industry that feature these principles and technologies.

关键词： Fault-tolerant systems field-programmable gate arrays radiation effects reconfigurable architectures satellites space radiation

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RFNN controlled sensorless induction spindle motor drive

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ELECTRIC POWER SYSTEMS RESEARCH 2004年第3期70卷 211-222页

作者： Lin, FJ Wang, DH Huang, PK Natl Dong Hwa Univ Dept Elect Engn Hualien 974 Taiwan

A sensorless induction spindle motor drive using synchronous PWM (SPWM) and dead-time compensator with recurrent fuzzy-neural network (RFNN) speed controller is proposed in this study for advanced spindle motor applications. First, the operating principles of a new type SPWM technique and the circuit of dead-time compensator using field-programmable gate arrays (FPGA) are described. Then, a speed observer based on a modified Luenberger observer is adopted to estimate the rotor speed. Moreover, since the control characteristics and motor parameters for a high-speed induction spindle motor drive are time-varying, an RFNN speed controller is developed to reduce the influence of parameter uncertainties and external disturbances. In addition, the RFNN is trained on-line using a delta adaptation law. Finally, the performance of the proposed sensorless induction spindle motor drive system is demonstrated using some simulated and experimental results. (C) 2003 Elsevier B.V. All rights reserved.

关键词： RFNN-1 speed controller field-programmable gate arrays dead-time compensator

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Reconfigurable hardware solution to parallel prefix computation

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JOURNAL OF SUPERCOMPUTING 2008年第1期43卷 43-58页

作者： Park, Jin Hwan Dai, H. K. SUNY Albany Dept Comp Sci New Paltz NY 12561 USA Oklahoma State Univ Dept Comp Sci Stillwater OK 74078 USA

This paper presents the design and implementation of an efficient reconfigurable parallel prefix computation hardware on field-programmable gate arrays (FPGAs). The design is based on a pipelined dataflow algorithm, and control logic is added to reconfigure the system for arbitrary parallelism degree. The system receives multiple input streams of elements in parallel and produces output streams in parallel. It has an advantage of controlling the degree of parallelism explicitly at run time. The time complexity of the design is O(d+(N-d)/d), where d and N are parallelism degree and stream size, respectively. When the stream size is sufficiently larger than the initial trigger time of the pipeline (d), the time complexity becomes O(N/d). Unlike the prefix computation circuits found in the literature, the design is scalable for different problem sizes including unknown sized data. The design is modular based on a finite state machine, and implemented and tested for target FPGA devices Xilinx Spartan2S XC2S300EFT256-6Q and XC2S600EFG676-6.

关键词： parallel prefix computation reconfigurable hardware field-programmable gate arrays dataflow pipeline

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