Although the reliability and robustness of the AES protocol have been deeply proved through the years, recent research results and technology advancements are rising serious concerns about its solidity in the (quite n...
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ISBN:
(纸本)9781479942930
Although the reliability and robustness of the AES protocol have been deeply proved through the years, recent research results and technology advancements are rising serious concerns about its solidity in the (quite near) future. In this context, we are proposing an extension of the AES algorithm in order to support longer encryption keys (thus increasing the security of the algorithm itself). In addition to this, we are proposing a set of parametric implementations of this novel extended protocols. These architectures can be optimized either to minimize the area usage or to maximize their performance. Experimental results show that, while the proposed implementations achieve a throughput higher than most of the state-of-the-art approaches and the highest value of the Performance Area metric when working with 128-bit encryption keys, they can achieve a 84x throughput speed-up when compared to the approaches that can be found in literature working with 512-bit encryption keys.
This paper presents a runtime system for reconfigurable accelerators that supports elastic management: it enables effective sharing of accelerator resources across multiple applications. For each application, this run...
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ISBN:
(纸本)9781479942930
This paper presents a runtime system for reconfigurable accelerators that supports elastic management: it enables effective sharing of accelerator resources across multiple applications. For each application, this runtime system allocates an appropriate amount of resources to satisfy its quality-of-service requirements, while minimising the overall execution time for a collection of applications. The effectiveness of this runtime system is due to a set of scheduling algorithms and strategies customised for different types of workloads. We demonstrate our approach by implementing a dynamic Monte Carlo bond options pricing design.
Embedded systems are shaping a new world. There is no sector immune to their adoption and the effects in the long term are unpredictable and fascinating. Embedded systems are designed by embedded system engineers. Wha...
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ISBN:
(纸本)9781479968435
Embedded systems are shaping a new world. There is no sector immune to their adoption and the effects in the long term are unpredictable and fascinating. Embedded systems are designed by embedded system engineers. What technical education and what kind of practical skills these new engineers will need? This is a complex and unanswered question. In this paper we describe our proposal to equip engineering students with knowledge and experience: REPTAR. REPTAR (Reconfigurable Embedded Platform for Training And Research) is a feature rich complex embedded system designed for giving the opportunity to tomorrow's engineers of having hands-on experience on modern technologies and learning by doing. As a side effect REPTAR revealed itself as an invaluable tool for rapid prototyping and research explorations.
Electronic trading in global markets and exchanges requires sophisticated communication and data management systems. Novel computational infrastructures and trading strategies are required to support the massive amoun...
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ISBN:
(纸本)9781479923809
Electronic trading in global markets and exchanges requires sophisticated communication and data management systems. Novel computational infrastructures and trading strategies are required to support the massive amount of incoming streaming data, where the main problem is in latency management. Multi-agent Systems have been recognized as a promising solution to address complex problems in many areas such as biology, social sciences and financial markets and may provide powerful and flexible solutions for implementing trading engines. In addition, reconfigurable hardware based on Field Programmable Gate Arrays (FPGAs) offers many important performance benefits over software implementations, such as reducing decision making latency and high-throughput data processing. Robust and scalable trading engines can be developed by leveraging the benefits of reconfigurable FPGA platforms. This paper presents a multi-agent architecture in reconfigurable hardware for financial applications and the implementation of a trading engine for pre-trade analysis as a validation scenario. Performance results show that calculation of technical indicators and trading strategy evaluation to generate trading signals with a latency of 550 ns is achievable.
In ultrasound (US) research, a key role is currently played by open platforms, i.e. flexible scanners with unlimited access to raw echo-data, which facilitate the implementation and experimental test of new echographi...
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ISBN:
(纸本)9781479968435
In ultrasound (US) research, a key role is currently played by open platforms, i.e. flexible scanners with unlimited access to raw echo-data, which facilitate the implementation and experimental test of new echographic methods. The methods proposed by research laboratories are increasingly demanding in terms of computational power and number of transmit/receive channels necessary for a suitable control of US array probes. In this paper, the basic module of a new 256-channel open platform is described. Such module, called Front-end (FE) board, integrates all of the electronics to simultaneously control 32 probe elements. Each FE board hosts four analog front-end chips, two DSPs and one FPGA, and is connected to the other boards in a ring with total I/O bandwidth of 80 Gbit/s full-duplex.
Nowadays, high-speed computations are mandatory for financial and insurance institutes to survive in competition and to fulfill the regulatory reporting requirements that have just toughened over the last years. A maj...
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ISBN:
(纸本)9781479923809
Nowadays, high-speed computations are mandatory for financial and insurance institutes to survive in competition and to fulfill the regulatory reporting requirements that have just toughened over the last years. A majority of these computations are carried out on huge computing clusters, which are an ever increasing cost burden for the financial industry. There, state-of-the-art CPU and GPU architectures execute arithmetic operations with pre-defined precisions only, that may not meet the actual requirements for a specific application. Reconfigurable architectures like field programmable gate arrays (FPGAs) have a huge potential to accelerate financial simulations while consuming only very low energy by exploiting dedicated precisions in optimal ways. In this work we present a novel methodology to speed up multilevel Monte Carlo (MLMC) simulations on reconfigurable architectures. The idea is to aggressively lower the precisions for different parts of the algorithm without loosing any accuracy at the end. For this, we have developed a novel heuristic for selecting an appropriate precision at each stage of the simulation that can be executed with low costs at runtime. Further, we introduce a cost model for reconfigurable architectures and minimize the cost of our algorithm without changing the overall error. We consider the showcase of pricing Asian options in the Heston model. For this setup we improve one of the most advanced simulation methods by a factor of 3-9x on the same platform.
This paper describes an efficient hardware implementation of a cross-correlation algorithm on a Field-Programmable Gate Array (FPGA) platform with the purpose of visually identifying coins. This method has the ability...
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ISBN:
(纸本)9789531841993
This paper describes an efficient hardware implementation of a cross-correlation algorithm on a Field-Programmable Gate Array (FPGA) platform with the purpose of visually identifying coins. This method has the ability to compare images obtained via a video camera with those stored in memory, thereby, accepting/rejecting coins-under-test at the very high-speed demanded by today's coin validation mechanisms. In addition, the user is offered the option to refresh the FPGA memory, i. e. add/remove coin images, on-site as well as store the test results on a host-machine if desired so. The implementation described here constitutes part of a wider coin-validation system that utilises multiple techniques, such as this, operating in-parallel with the sole purpose of Euro-coin identification at an acceptable performance to today's standards and criteria.
A novel test approach for interconnect resources (IRs) in field programmable gate arrays (FPGA) has been *** the test approach,SBs (switch boxes) of IRs in FPGA has been utilized to test ***,configurable logic blocks ...
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A novel test approach for interconnect resources (IRs) in field programmable gate arrays (FPGA) has been *** the test approach,SBs (switch boxes) of IRs in FPGA has been utilized to test ***,configurable logic blocks (CLBs) in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated *** a result,IRs can be scanned maximally with minimum configuration *** the experiment,an in-house developed FPGA test system based on system-on-chip (SoC) hardware/software verification technology has been applied to test XC4000E family of *** experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.
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