This paper presents a method of using FPGA to realize IIR digital *** method used full parallel distributed algorithm to reduce the hardware circuit scale on the premise of guaranteeing real time and to solve the prob...
详细信息
This paper presents a method of using FPGA to realize IIR digital *** method used full parallel distributed algorithm to reduce the hardware circuit scale on the premise of guaranteeing real time and to solve the problem of floating point calculation in FPGA using fixed-pointbinary *** a second-order IIR digital filter as an example,this paper used hierarchical method to design the digital filter and its function modules and to verify the hardware circuit through *** results showed that the design of IIR digital filter method has good real-time performance and the hardware circuit size is *** calculation of fixed-point binary number can control the filtering precision effectively,and the lookup table structure changed conveniently,which shows the flexibility of the design.
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