Various kinds of high bandwidth architecture using the embedded DRAM technology have been presented previously. In most cases, they use wide bus implementation and/or fast bus speed, that both have the penalty of die ...
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Various kinds of high bandwidth architecture using the embedded DRAM technology have been presented previously. In most cases, they use wide bus implementation and/or fast bus speed, that both have the penalty of die area and much power consumption at the same time. The proposing single-ended read-modify-write bus increases the bandwidth twice as high, while it maintains the same bus size and the same bus speed. The data-bus comprises 1 k-bit read-bus and 1 k-bit write-bus that each works concurrently, and has amplitude from 0 V to 1 V, hence the measured power consumption is only 0.3 W at a frequency of 166 MHz: A programmable page-size reduces the page miss-rate and efficiently improves the bandwidth that is comparable to the wide bus and fast speed approach. All the proposing features are implemented on a 3D frame-buffer to achieve 42.4 G-BPS bandwidth.
作者：
LEMKIN, PLIPKIN, LImage Processing Unit
Division of Cancer Biology and Diagnosis National Center Institute National Institute of Health Bethesda MD 20205 USA
This paper presents an example of a distributed monitor system, BMON-2, which was developed and is in daily use in a biological image processing environment. Useful aspects of such a system are discussed, particularly...
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This paper presents an example of a distributed monitor system, BMON-2, which was developed and is in daily use in a biological image processing environment. Useful aspects of such a system are discussed, particularly those which make for easier biologist-user interaction and system extensibility. The principles of extension of the distributed monitor to a time-shared computer system is outlined.
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