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Toward Reliable Programmable Logic Controller function block diagrams

IEEE ACCESS 2021年 9卷 166137-166146页

作者： Zhao, Jianyong Tao, Zhe Hangzhou Dianzi Univ Inst Intelligent & Software Technol Hangzhou 310018 Peoples R China

Programmable logic controllers (PLCs) are widely used in industrial electronic systems. With the augmenting complexity of system, the reliability poses a crucial challenge in safety critical applications. This paper proposes a formal modeling and verification approach for programming function block diagrams. function block diagrams are formalized in a logic specification system. We consider the equivalence checking problem which occurs frequently between design implementations under different performance constraints. We present a novel method to harness a powerful co-induction proof strategy with bisimulation to establish the equivalence in a higher-order logic theorem proving system. We validate the effectiveness of our approach by a real industry application example with key scenarios. The soundness and the completeness of our approach are substantiated.

关键词： Real-time systems Model checking Elevators Programming Computer languages Testing Syntactics Bisimulation function block diagram programmable logic controller

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Oeritte: User-Friendly Counterexample Explanation for Model Checking

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IEEE ACCESS 2021年 9卷 61383-61397页

作者： Ovsiannikova, Polina Buzhinsky, Igor Pakonen, Antti Vyatkin, Valeriy ITMO Univ Comp Technol Lab St Petersburg 197101 Russia Aalto Univ Dept Elect Engn & Automat Espoo 02150 Finland VTT Tech Res Ctr Finland Ltd Espoo 02044 Finland Lulea Tekniska Univ Dept Comp Sci Comp & Space Engn S-97187 Lulea Sweden

Thorough verification is a part of the design process of instrumentation and control systems if they must comply with crucial safety requirements. Model checking can be applied to the formal model of such a system to reason about its correctness based on the specification provided. When a violation occurs, the model checking tool outputs the proof of the violation in the form of a failure trace, which represents a state sequence of system model transitions where the requirement does not hold. This sequence, however, even for modular systems, is a mere table of values. Due to the lack of any insights into the inner model processes and structures that caused a problem, the debugging process of the formal model becomes time and effort consuming. The tool presented in this paper, Oeritte, is aimed at assisting the analyst in this challenge. It implements a method for automatic visual counterexample explanation which includes reasoning both over the falsified LTL formula and over the NuSMV function block diagram of the formal model of the system. The tool is applied to an industrial-sized safety control system of a nuclear power plant.

关键词： Tools Model checking Input variables Delays Visualization Safety Power generation Counterexample explanation counterexample visualization function block diagram NuSMV user-friendly model checking

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Automated test generation using model checking: an industrial evaluation

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INTERNATIONAL JOURNAL ON SOFTWARE TOOLS FOR TECHNOLOGY TRANSFER 2016年第3期18卷 335-353页

作者： Enoiu, Eduard P. Causevic, Adnan Ostrand, Thomas J. Weyuker, Elaine J. Sundmark, Daniel Pettersson, Paul Malardalen Univ Vasteras Sweden Swedish Inst Comp Sci Stockholm Sweden Software Engn Res Consultant Vasteras Sweden

In software development, testers often focus on functional testing to validate implemented programs against their specifications. In safety-critical software development, testers are also required to show that tests exercise, or cover, the structure and logic of the implementation. To achieve different types of logic coverage, various program artifacts such as decisions and conditions are required to be exercised during testing. Use of model checking for structural test generation has been proposed by several researchers. The limited application to models used in practice and the state space explosion can, however, impact model checking and hence the process of deriving tests for logic coverage. Thus, there is a need to validate these approaches against relevant industrial systems such that more knowledge is built on how to efficiently use them in practice. In this paper, we present a tool-supported approach to handle software written in the function block diagram language such that logic coverage criteria can be formalized and used by a model checker to automatically generate tests. To this end, we conducted a study based on industrial use-case scenarios from Bombardier Transportation AB, showing how our toolbox CompleteTest can be applied to generate tests in software systems used in the safety-critical domain. To evaluate the approach, we applied the toolbox to 157 programs and found that it is efficient in terms of time required to generate tests that satisfy logic coverage and scales well for most of the programs.

关键词： Automated test generation Software testing Model checking UPPAAL Logic coverage safety-critical systems IEC 1131-3 FBD function block diagram Structured Text PLC Programmable Logic Controllers Model-based testing

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A PLC platform-independent structural analysis on FBD programs for digital reactor protection systems

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ANNALS OF NUCLEAR ENERGY 2017年 103卷 454-469页

作者： Jung, Sejin Yoo, Junbeom Lee, Young-Jun Konkuk Univ Seoul South Korea Korea Atom Energy Res Inst Daejeon South Korea

FBD (function block diagram) has been widely used to implement safety-critical software for PLC (programmable logic controller)-based digital nuclear reactor protection systems. The software should be developed strictly in accordance with safety programming guidelines such as NUREG/CR-6463. Software engineering tools of PLC vendors enable us to present structural analyses using FBD programs, but specific rules pertaining to the guidelines are enclosed within the commercial tools, and specific links to the guidelines are not clearly communicated. This paper proposes a set of rules on the structure of FBD programs in accordance with guidelines, and we develop an automatic analysis tool for FBD programs written in the PLCopen TC6 format. With the proposed tool, any FBD program that is transformed into an open format can be analyzed the PLC platform-independently. We consider a case study on FBD programs obtained from a preliminary version of a Korean nuclear power plant, and we demonstrate the effectiveness and potential of the proposed rules and analysis tool. (C) 2017 Elsevier Ltd. All rights reserved.

关键词： Structural analysis function block diagram PLC Guidelines

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FBDTester 2.0: Automated test sequence generation for FBD programs with internal memory states

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SCIENCE OF COMPUTER PROGRAMMING 2018年 163卷 115-137页

作者： Song, Jiyoung Jee, Eunkyoung Bae, Doo-Hwan Korea Adv Inst Sci & Technol 291 Daehak Ro Daejeon 34141 South Korea

As function block diagram (FBD) programs are used to implement safety-critical systems such as nuclear reactor protection systems, it is crucial to generate effective test cases. FBD programs are running on programmable logic controllers (PLCs) that execute the programs repeatedly within a particular scan time. Among the elements of FBD programs, function blocks and feedback variables save the inputs or outputs of the previous scan cycle into internal memories. The data stored in the internal memory are used to operate the function blocks of the next scan cycle. Researchers have recently developed an automated test generation technique aiming to satisfy several structural test coverage criteria for FBD programs. Among them, Jee et al.'s approach has an advantage of generating tests from FBD programs without requiring any intermediate models. However, test sequence generation for FBD programs with internal memory states was not fully automated in Jee et al.'s approach. This paper extends Jee et al.'s work by generating test sequences from FBD programs with internal memory states in a fully automated manner. The key technique involves explicitly unwinding FBD programs and solving the test requirements using an SMT solver. We conduct experiments on increasing the coverage of test requirements by unwinding cycles and evaluating the effectiveness of the test set using mutation analysis with several subject programs, including a real-world reactor protection system. The experimental results show that the proposed approach is able to generate effective test sequences for FBD programs. To demonstrate the efficiency of the proposed approach, we compared the test sequence generation time required for our approach with those for other approaches. The comparison results show that even excluding the generation time of test models of other approaches, the proposed approach increased the time-efficiency by more than 11 times. (C) 2018 Elsevier B.V. All rights reserved.

关键词： function block diagram Automated test sequence generation Structural testing SMT solver

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A data flow-based structural testing technique for FBD programs

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INFORMATION AND SOFTWARE TECHNOLOGY 2009年第7期51卷 1131-1139页

作者： Jee, Eunkyoung Yoo, Junbeom Cha, Sungdeok Bae, Doohwan Korea Univ Dept Comp Sci & Engn Seoul 136701 South Korea Korea Adv Inst Sci & Technol Dept EECS Div Comp Sci Taejon 305701 South Korea Konkuk Univ Div Comp Sci & Engn Seoul 143701 South Korea

With increased use of programmable logic controllers (PLCs) in implementing critical systems, quality assurance became an important issue. Regulation requires structural testing be performed for safety-critical systems by identifying coverage criteria to be satisfied and accomplishment measured. Classical coverage criteria, based on control flow graphs, are inadequate when applied to a data flow language function block diagram (FBD) which is a PLC programming language widely used in industry. We propose three structural coverage criteria for FBD programs, analyze relationship among them, and demonstrate their effectiveness using a real-world reactor protection system. Using test cases that had been manually prepared by FBD testing professionals, our technique found many aspects of the FBD logic that were not tested sufficiently. Domain experts, having found the approach highly intuitive, found the technique effective. (C) 2009 Elsevier B.V. All rights reserved.

关键词： Software testing Structural testing Test coverage criteria Programmable logic controller function block diagram

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Model-Based Test Suite Generation for function block diagrams using the UPPAAL Model Checker

Model-Based Test Suite Generation for Function Block Diagram...

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IEEE International Conference on Software Testing, Verification and Validation Workshops

作者： Eduard Paul Enoiu Daniel Sundmark Paul Pettersson Malardalen Real-Time Research Centre (MRTC) Malardalen University

ISBN: (纸本)9781479913244

A method for model-based test generation of safety-critical embedded applications using Programmable Logic Controllers and implemented in a programming language such as function block diagram (FBD) is described. The FBD component model is based on the IEC 1131 standard and it is used primarily for embedded systems, in which timeliness is an important property to be tested. Our method involves the transformation of FBD programs with timed annotations into timed automata models which are used to automatically generate test suites. Specifically we demonstrate how to use model transformation for formalization and model-checking of FBD programs using the UPPAAL tool. Many benefits emerge from this method, including the ability to automatically generate test suites from a formal model in order to ensure compliance to strict quality requirements including unit testing and specific coverage measurements. The approach is experimentally assessed on a train control system in terms of consumed resources.

关键词： function block diagram Plc Model-based testing Timed automata Test-suite generation Structural coverage

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A BEHAVIOR-PRESERVING TRANSLATION FROM FBD DESIGN TO C IMPLEMENTATION FOR REACTOR PROTECTION SYSTEM SOFTWARE

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NUCLEAR ENGINEERING AND TECHNOLOGY 2013年第4期45卷 489-504页

作者： Yoo, Junbeom Kim, Eui-Sub Lee, Jang-Soo Konkuk Univ Div Comp Sci & Engn Seoul 143701 South Korea Korea Atom Energy Res Inst Man Machine Interface Syst Team Taejon 305353 South Korea

Software safety for nuclear reactor protection systems (RPSs) is the most important requirement for the obtainment of permission for operation and export from government authorities, which is why it should be managed with well-experienced software development processes. The RPS software is typically modeled with function block diagrams (FBDs) in the design phase, and then mechanically translated into C programs in the implementation phase, which is finally compiled into executable machine codes and loaded on RPS hardware - PLC (Programmable Logic Controller). Whereas C Compilers are fully-verified COTS (Commercial Off-The-Shelf) software, translators from FBDs to C programs are provided by PLC vendors. Long-term experience, experiments and simulations have validated their correctness and function safety. This paper proposes a behavior-preserving translation from FBD design to C implementation for RPS software. It includes two sets of translation algorithms and rules as well as a prototype translator. We used an example of RPS software in a Korean nuclear power plant to demonstrate the correctness and effectiveness of the proposed translation.

关键词： Behavior-Preserving Translation Programmable Logic Controller Translator function block diagram C Program

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Feature-Oriented Control Programming 25

Feature-Oriented Control Programming

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25th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA)

作者： Fors, Niklas Theorin, Alfred Robertz, Sven Gestegard Hedin, Gorel Lund Univ Dept Comp Sci Lund Sweden ABB Ind Automat Malmo Sweden

ISBN: (纸本)9781728189567

Managing variability in control programs often requires code duplication or that all variants are anticipated in advance. In this paper, we present a new approach to obtaining modular functionality reuse across variants. Using the language mechanisms diagram inheritance and connection interception, a feature model and an interactive feature-selection wizard can be automatically derived from the control program.

关键词： function block diagram feature model reuse inheritance intercept

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A New FPGA Based Green Controller Using FBD and HLS 4

A New FPGA Based Green Controller Using FBD and HLS

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4th International Conference on Renewable Energy Research and Applications (ICRERA)

作者： Morimoto, Kenichi Shibata, Yuichiro Shirakura, Yudai Maruta, Hidenori Kurokawa, Fujio Nobe, Masanori Tanaka, Masaharu Nagasaki Univ 1-14 Bunkyo Machi Nagasaki 8528521 Japan Mitsubishi Hitachi Power Syst LTD Naka Ku Yokohama Kanagawa 2208401 Japan Mitsubishi Heavy Ind Co Ltd Minato Ku Tokyo 1088225 Japan

ISBN: (纸本)9781479999828

For the renewable energy system, the power conservation and the low heat emission of the control system are big issue. Since those energy plants are installed in the natural environment which is inconvenient for the maintenance, it is very important that the control systems are supplied and maintained for long term without any development risk. The performance of the current CPU depends on the number of cores. The internal architecture is changed every time by the generation alternation. Both the development risk and the maintenance risk of the control systems become higher, and the product life cycle becomes shorter than before. The industrial systems for the infrastructures as well as for the renewable energy equipment are expected to maintain both the software and the hardware which have certain field records. The FPGA is watched, because of its low power consumption, and because of the inheritability of the HDL code. This paper presents a new FPGA based green controller by the approach of using the function block diagram which is suitable for the renewable energy plant. The approach applies the High Level Synthesis to each function block. Its basic behavior is confirmed by a simple tank level control simulation. It is clarified that the reuse of the FPGA resource is an important issue. Also the architecture which reuse the FPGA resources is presented against the issue. The performance is estimated.

关键词： FPGA energy saving control system reliability function block diagram high level synthesis

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