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Guided modes in graphene waveguides with magnetic-electric barrier

APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING 2012年第1期106卷 41-46页

作者： He, Ying Huang, Weide Yang, Yanfang Li, Chunfang Shanghai Univ Dept Phys Coll Sci Shanghai 200444 Peoples R China

An analysis of guided modes in graphene waveguides in the presence of magnetic-electric barrier is presented. The graphene waveguide is controlled by the gate voltages and the magnetic field by depositing two parallel ferromagnets on a dielectric layer. Both in the classical motion and Klein tunneling cases, the fundamental modes exist with the applied magnetic field. The electron wave propagation can be modulated in two different ways by changing the magnetic intensity or the incident energy. We hope that these characteristics can provide potential applications in the graphene-based waveguide devices.

关键词： WAVEGUIDES GRAPHENE ELECTROMAGNETISM gate array circuits TUNNELING (Physics) MAGNETIC fields FORCE & energy

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Defect-centric perspective of time-dependent BTI variability

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MICROELECTRONICS RELIABILITY 2012年第9-10期52卷 1883-1890页

作者： Toledano-Luque, M. Kaczer, B. Franco, J. Roussel, Ph J. Grasser, T. Groeseneken, G. IMEC Kapeldreef 75 B-3001 Louvain Belgium Katholieke Univ Leuven ESAT B-3001 Louvain Belgium Vienna Univ Technol Inst Microelect A-1040 Vienna Austria

With the continuous downscaling of CMOS device dimensions, (i) The number of gate oxide defects in each device decreases to a numerable level, while their relative impact on the device characteristics increases. (ii) The properties of each defect, such as its capture and emission times and its impact, are voltage and/or temperature dependent and widely distributed. (iii) The occupation kinetics of each defect is known to be stochastic. All of these result in each of the nominally identical nm-scaled devices behaving very differently during operation, resulting in increasing time-dependent variability (heteroskedasticity). Consequently, the lifetime of nm-sized devices cannot be predicted individually, but can be described in terms of time- (or workload-) dependent distributions. (C) 2012 Elsevier Ltd. All rights reserved.

关键词： POINT defects COMPLEMENTARY metal oxide semiconductors gate array circuits FIELD emission HETEROSCEDASTICITY ELECTRONIC apparatus & appliances

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Experimental determination of equivalent oxide thickness of gate insulators

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JOURNAL OF APPLIED PHYSICS 2002年第10期91卷 6571-6579页

作者： Hiraiwa, A Sakai, S Ishikawa, D Nakazawa, M Hitachi Ltd Device Dev Ctr Dept Proc Dev Tokyo 1988512 Japan

We propose an experimental method of determining the equivalent oxide thickness (EOT) of gate insulators based on the principle that the capacitance associated with the bandbendings in the Si substrate and the gate (Si capacitance) depends only on the Si surface field. To do this we experimentally obtained the Si surface field by using the capacitance-voltage (CV) integration method, and we used x-ray reflectometry to measure the physical thickness of thermal oxides. We then determined the relationship between the Si capacitance and the Si surface field. The relationship among the Si capacitance, the Si surface field, the EOT, and gate voltage minus the flatband voltage was also experimentally obtained. From these two relationships, we produce ideal CV curves for any given EOT and determined EOTs in such a way that the ideal CV curves fit best with the experimental results. Accordingly, our method is free of errors that accompany modeling the quantum mechanics of the gate electrode and Si substrate, and any errors that it does contain are independent of the film thickness. We further simplified the method for practical application by approximating the above relationships using rational polynomials. The results obtained by this simplified method were in good agreement with the experiments for the whole range of thicknesses. In contrast, the conventional quantum mechanical simulators produced CV curves that showed no small difference from the measured ones in the case of thin oxides in the 1-nm-thick range, and led to an overestimate of the EOT. Our method of EOT derivation provides an important basis for developing high-performance metal-oxide-semiconductor transistors. (C) 2002 American Institute of Physics.

关键词： OXIDES gate array circuits

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Impact of technology scaling on the 1/f noise of thin and thick gate oxide deep submicron NMOS transistors

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IEE PROCEEDINGS-circuits DEVICES AND SYSTEMS 2004年第5期151卷 415-421页

作者： Chew, KW Yeo, KS Chu, SF Chartered Semicond Mfg Ltd Singapore 738406 Singapore Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore

This study discusses the composite effect of channel length and gate oxide thickness scaling, coupled with the effect of gate dielectric nitridation on the 1/f noise of minimum channel length NMOS transistors. These transistors have been taken from four advance CMOS technologies with dual gate oxide thickness. The result shows that the current noise spectral density S-Id of a thin gate oxide transistor increases by approximately 1.5 orders of magnitude when scaling from 350 ran to 130 nm. This increase is closely correlated to the changeover from thermal oxides to nitrided oxides from 250 nm and below. This work also investigates the effect of nitridation on thick gate oxide transistors and compares them to their architecturally equivalent thin gate oxide non-nitrided counterpart from 350 nm technology. The comparison reveals that nitridation has increased the S-Id of architecturally equivalent thick gate oxide transistors from 250 nm to 130 nm technologies by a maximum of 1.25 orders of magnitude. The experimental 1/f noise trends have been verified with simulations using the BSIM3v3 flicker noise model.

关键词： MICROELECTRONICS NOISE METAL oxide semiconductor field-effect transistors NITRIC oxide gate array circuits SEMICONDUCTORS

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High-energy radiation etiects on subthreshold characteristics, transconductance and mobility of n-channel MOSFETs

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SEMICONDUCTOR SCIENCE AND TECHNOLOGY 2003年第12期18卷 1037-1042页

作者： Prakash, APG Ke, SC Siddappa, K Natl Dong Hwa Univ Dept Phys Hualien 97401 Taiwan Mangalore Univ Dept Phys Microtron Ctr Mangalagangothri 574199 India

The influence of 8 MeV electrons on the threshold voltage (V-TH), transconductance (g(m)) and mobility (mu) of n-channel depletion metal-oxide semiconductor field-effect transistors (MOSFETs) irradiated at gate bias, V-GS = +2, 0 and -2 V, has been studied in the dose range of 0.5-31 kGy. The measurements performed after irradiation showed considerable decrease in V-TH, g(m) and mu. The densities of interface trapped charge (DeltaN(it)) and oxide trapped charge (DeltaN(ot)) for irradiated devices have been estimated from the subthreshold measurements. It has been found that DeltaN(ot) is higher than DeltaN(it). The mobility of carriers (mu) in the n-channel was estimated from the peak transconductance (g(mPeak)) and it was found that mu decreased by around 68.5-73.5% after exposure to the total dose of 31 kGy. Mobility degradation coefficients due to interface traps (alpha(it)) and oxide trapped charge (alpha(ot)) were estimated and it was found that the mobility degradation was mainly due to DeltaN(it) and the effect of DeltaN(ot) was negligible.

关键词： METAL oxide semiconductor field-effect transistors RADIATION EPITAXY gate array circuits

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Applying the Handel-C design flow in designing an HMAC-hash unit on FPGAs

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 2006年第5期153卷 323-334页

作者： Khan, E. Watheq El-Kharashi, M. Gebali, F. Abd-El-Barr, M. Univ Victoria Dept Elect & Comp Engn Victoria BC Canada

An emerging system design methodology in designing a reconfigurable HMAC-hash unit is utilised. This methodology directly maps a design described in a high-level language, Handel-C, to field programmable gate array platforms. The Handel-C approach narrows the gap between performance and flexibility and thus, reduces the risk of translating a high-level prototype into hardware description languages. It allows for a high degree of flexibility from two viewpoints: the language level of abstraction and the hardware reconfiguration. A detailed case study is considered: a reconfigurable HMAC-hash unit that implements six standard hash functions: MD5, SHA-1, RIPEMD-160, HMAC-MD5, HMAC-SHA-1 and HMAC-RIPEMD-160. The performance of the designed unit has been enhanced by applying pipelining, parallelism and reconfigurability through the usage of the Handel-C methodology. The use of Handel-C resulted in the HMAC-hash unit architecture that is better in speed than most of the previously designed units. At the same time, the area cost for putting the six standard algorithms on the same hardware core is also kept to a minimum. It is found that the time required to design, implement and test the designed unit using this methodology is reasonably low compared with the time required using other design approaches.

关键词： SYSTEMS design gate array circuits PROGRAMMING languages (Electronic computers) COMPUTER input-output equipment PIPELINING (Electronics) SOFTWARE configuration management COMPUTER architecture ENGINEERING standards ALGORITHMS

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Bichromatic tuning of reflection bands in integrated CLC reflectors for optical switches, gates, and logic

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APPLIED PHYSICS B-LASERS AND OPTICS 2015年第3期118卷 379-385页

作者： Wu, Shing-Trong Fuh, Andy Ying-Guey Ho, Shau-Jung Li, Ming-Shian Natl Cheng Kung Univ Dept Phys Tainan 701 Taiwan Natl Cheng Kung Univ Inst Electroopt Sci & Engn Tainan 701 Taiwan Natl Cheng Kung Univ Adv Optoelect Technol Ctr Tainan 701 Taiwan

This study investigates the bichromatic tuning of cholesteric liquid crystal (CLC) reflection bands from reflectors containing chiral azo dopants. Because the chiral azo molecules change their helical twist power in reversible photoisomerization, the reflection bands of the CLCs are modulated using purple and green laser beams. The CLC reflectors are integrated into an optical gate that can be used to modulate output spectra. We also apply the integrated system in optical switching and logic.

关键词： CHOLESTERIC liquid crystals CHIRALITY AZO compounds REFLECTION (Optics) LIGHTING reflectors OPTICAL switches gate array circuits PHOTOISOMERIZATION

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A Quasi-3D Threshold Voltage Model for Dual-Metal Quadruple-gate MOSFETs

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Chinese Physics Letters 2014年第12期31卷 154-156页

作者： Visweswara Rao Samoju Satyabrata Jit Pramod Kumar Tiwarit Department of Electronics & Communication Engineering National Institute of Technology Rourkela 769008 India Department of Electronics Engineering Indian Institute of Technology (BHU) Varanasi 221005 India

Due to challenges with relentless scaling of conventional bulk complementary metal-oxide- semiconductor （CMOS） devices, non-conventional CMOS devices have been of great interest to scale metaboxide-semiconductor field effect transistors （MOSFETs） to the 32nm gate length and below effectively. Among non-conventional CMOS devices, quadruple-gate （QG） MOSFETs have been gaining interest because they are sup- posed to provide excellent electrostatic controllability for ultra-large-scale integration （ULSI） applications. A number of attempts have been made to analyze QG MOSFETs analytically with a great amount of success. Sharma et al. have presented an an- alytical threshold voltage model for QG MOSFETs using an isomorphic polynomial function for solv- ing the 3D Poisson equation. Chiang has presented a number of models of scaling length,threshold voltage and subthreshold current for QG MOS- FETs adopting a concept of the so-called equivalent number of gates （ENGs）.

关键词： METAL oxide semiconductor field-effect transistors THRESHOLD voltage MATHEMATICAL models CATHODES COMPUTER simulation gate array circuits

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A Controlled Phase gate with Nitrogen-Vacancy Centers in Nanocrystal Coupled to a Silica Microsphere Cavity

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Chinese Physics Letters 2010年第6期27卷 5-8页

作者： XUE Peng Department of Physics Southeast University Nanjing 211189

We show how a controlled phase gate, induced by adiabatic passage of dark states, can be implemented with the nitrogen-vacancy defects in nanocrystal coupled to the optical whispering gallery mode in a silica microsphere cavity. The gate presented is robust to the fluctuations of the experimental parameters compared to the dynamical and geometric phases gates. The feasibility of this scheme is characterized by exact numerical simulations that incorporate various sources of experiment noise. The results demonstrate the practicality by way of current experimental technologies.

关键词： gate array circuits NITROGEN POINT defects NANOCRYSTALS SILICA NUMERICAL analysis SIMULATION methods & models

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Non-Volatile Threshold Adaptive Transistors with Embedded RRAM

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Chinese Physics Letters 2014年第10期31卷 153-156页

作者：邓宁贾弘扬吴畏吴华强 Institute of Microelectronics Tsinghua University Beijing 100084

We propose a novel nonvolatile threshold adaptive transistor （TAT） for neuromorphic circuits. The threshold adaptive transistor is achieved by embedding a resistive random-access memory （RRAM） material stack between the gate electrode and gate dielectric. During operation, the embedded RRAM device is kept at a high resistance state, which makes it act as a nonvolatile capacitor. The threshold could be nonlinearly adjusted by the voltage pulses applied on the gate of the transistor. We quantitatively estimate the range of the capacitance variation of the RRAM device. The threshold voltage of the TAT is simulated and shows expected variation. The simulated output of an inverter using a TAT shows a nonlinear adaptive behavior.

关键词： TRANSISTORS NONVOLATILE random-access memory THRESHOLD voltage EMBEDDING theorems gate array circuits

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