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ESD protection for thin gate oxides in 65 nm

MICROELECTRONICS RELIABILITY 2010年第1期50卷 26-31页

作者： Notermans, Guido Smedes, Theo Mrcarica, Zeljko de Jong, Peter Stephan, Ralph van Zwol, Hans Maksimovic, Dejan ST Ericsson CH-8045 Zurich Switzerland NXP Semicond NL-6535 AE Nijmegen Netherlands

Unexpected functional failures were found in the core of an IC, processed in a 65 nm technology with 1.8 nm gate oxide, after Machine Model (MM) testing, although a comprehensive rail-based protection scheme was applied. Failure analysis was performed including Obirch, backside de-processing, and SEM analysis to locate the failure in the gate oxide of several core NMOS transistors. Careful Transmission Line Pulse (TLP) measurements on NMOSTs with 1.8 nm oxides yields a mean BVox = 6.06 V and standard deviation of 0.18 V, after correction for MM test conditions. Comparison with a mean Vt1 = 5.35 V and a standard deviation of 0.15 V for ggNMOSTs shows that the tails of the BVox and Vt1 distributions overlap. This implies that connecting a gate to a drain diffusion does not guarantee adequate protection for a 1.8 nm gate oxide in a 65 nm technology. (C) 2009 Elsevier Ltd. All rights reserved.

关键词： ELECTRIC discharges gate array circuits FAILURE analysis (Engineering) INTEGRATED circuits SCANNING electron microscopy METAL oxide semiconductor field-effect transistors ELECTRIC lines STANDARD deviations

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New optimized Dual-Material (DM) gate design to improve the submicron GaN-MESFETs reliability in subthreshold regime

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MICROELECTRONICS RELIABILITY 2012年第6期52卷 958-963页

作者： Lakhdar, N. Djeffal, F. Univ Batna Dept Elect LEA Batna 05000 Algeria Univ Batna LEPCM Batna 05000 Algeria

In this paper, new Dual-Material-gate (DM) concept and optimization approach are proposed to improve the device immunity against the hot carrier and short channel effects (SCEs), and optimize the subthreshold electrical performance of the submicron Gallium Nitride (GaN)-MESFET. The 2D analytical analysis includes the modeling of the channel potential, subthreshold swing, threshold voltage, Drain-Induced Lowering Barrier (DIBL) and parasitic resistances. The influence of gate length and the work function of each gate region on subthreshold behavior was investigated using the developed analytical models. The developed analytical approaches are verified and validated by the good agreement found with the 2D numerical simulations for wide range of device parameters and bias conditions. The presented compact models are used to formulate the different objective functions, which are the pre-requisite of multiobjective genetic algorithms optimization, which will be used to optimize the device subthreshold performances. The optimized design can alleviate the critical problem and further improve the immunity of SCEs of submicron GaN-MESFET-based digital circuits for low power and high speed applications. (C) 2011 Elsevier Ltd. All rights reserved.

关键词： MATHEMATICAL optimization gate array circuits GALLIUM nitride ELECTRIC resistance METAL semiconductor field-effect transistors PERFORMANCE evaluation NUMERICAL analysis SIMULATION methods & models

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HMM-TLP correlation for system-efficient ESD design

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MICROELECTRONICS RELIABILITY 2012年第6期52卷 1012-1019页

作者： Notermans, Guido Bychikhin, Sergey Pogany, Dionyz Johnsson, David Maksimovic, Dejan ST Ericsson CH-8952 Schlieren Zh Switzerland Vienna Univ Technol Inst Solid State Elect A-1040 Vienna Austria High Power Pulse Instruments D-85540 Haar Germany

A linear correlation between 100 ns TLP and the second HMM peak current was found for several common types of protection devices. A detailed thermal analysis offers a straightforward explanation of the correlation factor in terms of pulse duration. It is found that the thermal effect of the first HMM peak can be ignored. The impact of non-thermal failure mechanisms, e.g. gate oxide breakdown due to an over-voltage, which may limit the validity of the correlation are explored for a complete system, which includes additional components. The results from this investigation are essential for proper application of the System-efficient ESD Design (SEED) methodology. (C) 2011 Elsevier Ltd. All rights reserved.

关键词： ELECTRIC discharges CORRELATION (Statistics) THERMAL analysis BREAKDOWN (Electricity) ELECTRONIC circuit design gate array circuits ELECTRIC potential

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Electrical properties of ferroelectric-gate FETs with SrBi₂Ta₂O₉ formed using MOCVD technique

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APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING 2012年第4期108卷 835-842页

作者： Yan, Kang Takahashi, Mitsue Sakai, Shigeki Natl Inst Adv Ind Sci & Technol Tsukuba Ibaraki 3058568 Japan

Ferroelectric-gate field-effect transistors (FeFETs) with a Pt/SrBi2Ta2O9/Hf-Al-O/Si gate stack were fabricated using the metal-organic chemical vapor deposition (MOCVD) technique to prepare the SrBi2Ta2O9 (SBT) ferroelectric layer. A good threshold voltage (V-th) distribution was found for more than 90 n-channel FeFETs in one chip with a 170 nm SBT layer owing to the good film uniformity of the SBT layer deposited by MOCVD. The average memory window (V-w(av)) and the standard deviations (sigma(thl), sigma(thr)) of the left- and right-side branches of the drain-gate voltage curves of the FeFETs yielded a V-w(av)/(sigma(thl) + sigma(thr)) value of 5.45, indicating that the FeFETs can be adapted for large-scale-integration. The electric field, the energy band profile in the gate stack, and the gate leakage current were also investigated at high gate voltages. We found that the effect of Fowler-Nordheim tunneling appeared under these conditions. Because of the tunneling injection and trapping of electrons into the gate insulators, the operation voltage ranges of the FeFETs were limited by this tunneling.

关键词： ELECTRIC properties of metals FERROELECTRICITY gate array circuits FIELD-effect transistors METAL organic chemical vapor deposition STRONTIUM compounds THRESHOLD voltage METALLIC oxides

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The role of a tensile stress bias for a sensitive silicon mechanical stress sensor based on a change in gate-induced-drain leakage current

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MICROELECTRONICS RELIABILITY 2012年第11期52卷 2847-2850页

作者： Lau, W. S. Yang, Peizhen Siah, S. Y. Chan, L. Nanyang Technol Univ Sch EEE Singapore 639798 Singapore Global Foundries Singapore 738406 Singapore

Mechanical stress sensors based on silicon piezoresistance have limited sensitivity. Mechanical stress sensors based on the on-current or off-current or threshold voltage of silicon MOS transistors also have limited sensitivity. In this paper, we report that the sensitivity of a silicon-based mechanical sensor can be significantly improved by simply monitoring the gate-induced-drain leakage (GIDL) current of an n-channel MOS transistor. The role of a tensile mechanical stress bias will also be discussed. (C) 2012 Elsevier Ltd. All rights reserved.

关键词： STRAINS & stresses (Mechanics) SILICON gate array circuits ELECTRIC leakage ELECTRIC resistance METAL oxide semiconductor field-effect transistors

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gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect

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MICROELECTRONICS RELIABILITY 2010年第5期50卷 607-609页

作者： Hung, H. J. Kuo, J. B. Chen, D. Yeh, C. S. Natl Taiwan Univ Dept Elec Eng Rm Taipei 10617 Taiwan UMC Hsinchu 300 Taiwan

This paper reports an analysis of floating body effect related gate tunneling leakage current behavior of the 40 nm PD SOI NMOS device using bipolar/MOS equivalent circuit approach. As confirmed by the experimentally measured data, the bipolar/MOS equivalent circuit approach could predict the gate tunneling leakage current behavior, which is strongly affected by the parasitic bipolar device in the floating body as observed from the perpendicular electric field along the path of the U-shaped edges of the poly-silicon gate. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： gate array circuits TUNNELING (Physics) ELECTRIC leakage SILICON-on-insulator technology METAL oxide semiconductor field-effect transistors BIPOLAR transistors ELECTRIC fields MICROELECTRONICS

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Neural Classifiers of Vibroacoustic Signals in Implementation on Programmable Devices (FPGA) - Comparison

ACTA PHYSICA POLONICA A

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ACTA PHYSICA POLONICA A 2011年第6A期119卷 946-949页

作者： Dabrowski, D. Cioch, W. Univ Sci & Technol Dept Mech & Vibroacoust PL-30059 Krakow Poland

The research includes comparative analysis of the effect of the recording of weight vectors and input data of selected neural classifiers with fixed-point numbers. Research has been conducted due to insufficient literature on the influence of such a recording on the correct classification of vibroacoustic signals by neural networks. This current issue was brought up in authors' earlier researches, concerning realization of neural classifiers on programmable logical devices field programmable gate array, with the application of fixed-point processor. During the analysis, three types of neural classifiers were compared in the tests: classifier based on neural network - length vector quantization, classifier using radial neural networks - radial basis functions, and third - counter propagation neural network. The problem stated was to recognize technical state of gear transmission DMA-1 in variable operating conditions. Vectors, based on estimates derived from processed vibroacoustic signals were used as teaching material.

关键词： COMPARATIVE studies NEURAL networks (Computer science) gate array circuits RADIAL basis functions APPROXIMATION theory

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Validity of Lamb-Dicke Approximations in Ion-Trap Systems

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Chinese Physics Letters 2010年第1期27卷 21-24页

作者：蓝海江张淼韦联福 Department of Physics Liuzhou Teachers' College Liuzhou 545003 Quantum Optoeleetronics Laboratory Southwest Jiaotong University Chengdu 610031

The Lamb-Dicke （LD） approximation （LDA） is usually utilized to simplify the treatments for the dynamics of ion-trap systems, where the so-called LD parameters should be sufficiently small. In this Letter, based on the quantum dynamics of a single trapped ion beyond the LDA, we discuss the fidelities of the control-NOT （CNOT） gate generated by performing the usual LDA. It is shown that the fidelity of the generated CNOT gate under the LDA is sufficiently high for the current LD experiments, e.g., it reaches 99.9% for η=0.20. The validity of the LDA is also discussed by calculating these fidelities for slightly larger LD parameters, e.g., η=0.4, etc.

关键词： APPROXIMATION theory ION traps QUANTUM theory gate array circuits EXPERIMENTS MATHEMATICAL physics

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Polarization phase gate and three-photon GHZ state using coherently enhanced Kerr nonlinearity

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OPTICS COMMUNICATIONS 2010年第6期283卷 1017-1021页

作者： Ba, Nuo Wan, Ren-Gang Jiang, Bo-Nan Wang, Heng Wang, Da-Wei Zhang, Yan Wu, Jin-Hui Jilin Univ Coll Phys Changchun 130023 Peoples R China

We study the nonlinear optical response of a five-level atomic system in the regimes of electromagnetically induced transparency and coherent Raman gain, corresponding to two different schemes of light-atom interaction, Our analytical and numerical results show that greatly enhanced Kerr nonlinearity and efficient cross phase modulation may be achieved between a weak probe field and a weak signal field. The cross phase modulation via Kerr nonlinearity is then exploited toward the realization of a polarization quantum phase gate and the generation of a three-photon GHZ state. (C) 2009 Elsevier B.V. All rights reserved.

关键词： OPTICAL polarization gate array circuits PHOTONS COHERENCE (Optics) KERR electro-optical effect NONLINEAR optics OPTICAL communications ELECTROMAGNETIC induction NUMERICAL analysis

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Unit capacitor array based SAR ADC

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MICROELECTRONICS RELIABILITY 2013年第3期53卷 505-508页

作者： Pun, Kong-Pang Sun, Lei Li, Bing Chinese Univ Hong Kong Dept Elect Engn Shatin Hong Kong Peoples R China

This paper proposes a new successive approximation register analog-to-digital converter by using a unit capacitor array to implement the digital-to-analog converter. Under the same differential non-linearity specification, the proposed method can consume orders of magnitude less switching power and chip area than all existing solutions, including those using a binary weighted capacitor array (with or without a bridge capacitor) and those using a split capacitor array. The claimed benefits of the proposed method are verified by behavioral simulations. (C) 2012 Elsevier Ltd. All rights reserved.

关键词： ELECTROLYTIC capacitors ANALOG-to-digital converters MICROELECTRONICS SIMULATION methods & models gate array circuits DIGITAL electronics

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