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Deep-amorphization and solid-phase epitaxial regrowth processes for hybrid orientation technologies in SOI MOSFETs with thin body

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MICROELECTRONICS RELIABILITY 2012年第11期52卷 2602-2608页

作者： Ohata, A. Bae, Y. Cristoloveanu, S. Signamarcheix, T. Widiez, J. Ghyselen, B. Faynot, O. Clavelier, L. Osaka City Univ Dept Elect Engn Osaka 5588585 Japan Uiduk Univ Dept Elect Gyeongju South Korea Grenoble INP Minatec IMEP LAHC UMR 5130 F-38016 Grenoble 1 France CEA LETI MINATEC F-38054 Grenoble France SOITEC F-38190 Bernin France

Local Deep-Amorphization (DA) and subsequent Solid-Phase Epitaxial Regrowth (SPER) are envisioned for the co-integration of devices with hybrid surface orientation. The impact of these processes on the electrical characteristics of p-channel MOSFETs with 20 nm thick film and HfO2 gate insulator/metal gate along the < 1 1 0 > direction on a (1 1 0) substrate is studied. No deterioration of transconductance and subthreshold swing at the front or back channels was induced by DA/SPER. The transconductance enhancement for the front and back channels on (1 1 0) substrates reaches +200% and +230% gain, respectively. For these transistors, we also discuss the variation of the external resistance and their operation in double-gate mode. (C) 2012 Elsevier Ltd. All rights reserved.

关键词： AMORPHOUS substances EPITAXY SILICON-on-insulator metal oxide semiconductor field-effect transistors SURFACES (Technology) gate array circuits ELECTRIC insulators & insulation SUBSTRATES (Materials science)

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An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices

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MICROELECTRONICS RELIABILITY 2012年第3期52卷 519-524页

作者： Trevisoli, Renan Doria Martino, Joao Antonio Simoen, Eddy Claeys, Cor Pavanello, Marcelo Antonio Univ Sao Paulo LSI PSI USP BR-05508900 Sao Paulo Brazil IMEC B-3001 Louvain Belgium Katholieke Univ Leuven EE Dept B-3001 Louvain Belgium Ctr Univ FEI Dept Elect Engn BR-09850901 Sao Bernardo Do Campo Brazil

Triple-gate devices are considered a promising solution for sub-20 nm era. Strain engineering has also been recognized as an alternative due to the increase in the carriers mobility it propitiates. The simulation of strained devices has the major drawback of the stress non-uniformity, which cannot be easily considered in a device TCAD simulation without the coupled process simulation that is time consuming and cumbersome task. However, it is mandatory to have accurate device simulation, with good correlation with experimental results of strained devices, allowing for in-depth physical insight as well as prediction on the stress impact on the device electrical characteristics. This work proposes the use of an analytic function, based on the literature, to describe accurately the strain dependence on both channel length and fin width in order to simulate adequately strained triple-gate devices. The maximum transconductance and the threshold voltage are used as the key parameters to compare simulated and experimental data. The results show the agreement of the proposed analytic function with the experimental results. Also, an analysis on the threshold voltage variation is carried out, showing that the stress affects the dependence of the threshold voltage on the temperature. (C) 2011 Elsevier Ltd. All rights reserved.

关键词： gate array circuits SIMULATION methods & models ELECTRIC potential CORRELATION (Statistics) ANALYTIC functions THRESHOLD voltage

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Ultrathin oxynitride films on strained SiGe layers by a three-step NO/O₂/NO process

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SOLID-STATE ELECTRONICS 2004年第1期48卷 91-97页

作者： Samanta, SK Chatterjee, S Maikap, S Maiti, CK Indian Inst Technol Dept Elect Kharagpur 721302 W Bengal India Indian Inst Technol ECE Kharagpur 721302 W Bengal India

A technique for the formation of gate quality ultrathin oxynitride films at a low temperature (150 degreesC) by a three-step (NO/O-2/NO) process in a microwave plasma is reported. Oxynitride films have been grown on strained-Si0.74Ge0.26 films. The mechanism of nitrogen incorporation has been studied in detail. The electrical properties of the oxynitride films have been characterized using a metal-insulator-semiconductor (MIS) structure. Capacitance-voltage (C V), conductance voltage (G-V), constant current and voltage stressing characteristics have been measured. It is shown that a NO/O-2/NO three-step process, in general, gives rise to better electrical properties and reliability compared to a single-step O-2- and NO-plasma grown oxide films. (C) 2003 Elsevier Ltd. All rights reserved.

关键词： Nitrides Thin films Microwave plasmas gate array circuits

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Effect of localised charges on nanoscale cylindrical surrounding gate MOSFET: Analog performance and linearity analysis

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MICROELECTRONICS RELIABILITY 2012年第6期52卷 989-994页

作者： Gautam, Rajni Saxena, Manoj Gupta, R. S. Gupta, Mridula Univ Delhi Dept Elect Sci Semicond Device Res Lab New Delhi 110021 India Univ Delhi Deen Dayal Upadhyaya Coll Dept Elect New Delhi 110015 India Maharaja Agrasen Inst Technol Dept Elect & Commun Engn New Delhi 110086 India

The paper presents a simulation study of Nanoscale Cylindrical Surrounding gate (SRG) MOSFET with localised interface charges. The objective of the present work is to study the performance degradation due to hot carrier induced/radiation induced/stress induced damage in the form of localised/fixed charges at the semiconductor/oxide interface of the device. Impact of fixed charges has been studied on the characteristics such as drain current, transconductance and its higher order terms, device efficiency and linearity FOMs. Effect of nature and extension of interface fixed charges has been discussed in detail through extensive simulation. Circuit reliability issues of the device are discussed in terms of DC bias point degradation. (C) 2011 Elsevier Ltd. All rights reserved.

关键词： ELECTRIC charge & distribution NANOELECTRONICS gate array circuits METAL oxide semiconductor field-effect transistors PERFORMANCE evaluation ELECTRIC currents SIMULATION methods & models INTERFACES (Physical sciences)

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Enhanced Total Ionizing Dose Hardness of Deep Sub-Micron Partially Depleted Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Field Effect Transistors by Applying Larger Back-gate Voltage Stress

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Chinese Physics Letters 2014年第12期31卷 82-84页

作者：郑齐文崔江维余学峰郭旗周航任迪远 Key Laboratory of Functional Materials and Devices for Special Environments Xinjiang Technical Institute of Physics and Chemistry Chinese Academy of Sciences Urumqi 830011 Xinjiang Key Laboratory of Electronic Information Material and Device Urumqi 830011 University of Chinese Academy of Sciences Beijing 100049

Owing to the fifll isolation and minimization of the silicon active volume, silicon-on-insulator （SOI） tech- nology has better resistance against transient ionizing effects like single event effects （SEE） or latch ***, the total ionizing dose （TID） irradiation responses of SOI transistors are more complex than bulk-silicon devices. In addition to the gate and par- asitic field leakage current, which are common to SOI and bulk-silicon devices, irradiation induced charges trapped in the SOI buried oxide （BOX） can also affect SOI device performance. Typically, there is a par- asitic edge transistor in the back-gate of SOI devices paralleled with the main transistor, which is formed by the corner region of the silicon island. Due to the high electric field induced by the back-gate voltage at the corner of the silicon island, the threshold of the parasitic edge transistor is lower than the main transistor, resulting in a sub-threshold hump in the transfer characteristic of the back-gate transistor. Even though the threshold of the parasitic edge tran- sistor is lower than the main transistor, it is still larger than zero, which has no effect on the front- gate of devices. However, the sub-threshold hump in the back-gate is the ＇Achilles heel＇ for total dose responses of deep sub-micron SOI n-type metal-oxide- semiconductor field-effect transistors （MOSFETs） iso- lated by shallow trench isolation （STI）. As reported in Refs., the threshold of the parasitic edge transis- tor is negative shifted by radiation-induced charges trapped in STI, leading to off-state leakage in the front-gate of devices.

关键词： METAL oxide semiconductor field-effect transistors SILICON-on-insulator technology IONIZATION (Atomic physics) HARDNESS ELECTRIC fields gate array circuits ELECTRIC potential

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Reliability evaluation for single event crosstalk via probabilistic transfer matrix

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MICROELECTRONICS RELIABILITY 2012年第7期52卷 1511-1514页

作者： Liu, Baojun Cai, Li Bai, Peng Peng, Weidong AF Engn Univ Inst Sci Xian 710051 Peoples R China AF Engn Univ Synthet Elect Informat Syst Res Dept Xian 710051 Peoples R China

To quantitatively analyze the influence on integrated circuits (ICs) by crosstalk and single event effects, the reliability of ICs under these effects was evaluated via probabilistic transfer matrix (PTM). The basic theory of PTM was briefly introduced. By modifying the right probability of gates in PTM, the influence from single event effect on the reliability was obtained. By considering the error probability of signal transportation through interconnects, the reliability under crosstalk was calculated. The results show that crosstalk and single event effects will both decrease the reliability of ICs. The farther from the output the gate is suffered from single event effect, the less significant influences on the reliability decreased. The crosstalk effects will bring worse influences on the reliability than single event effects. The technologies for improving reliability of ICs should take more attentions to the crosstalk effects and multi-single event effects. (C) 2012 Elsevier Ltd. All rights reserved.

关键词： CROSSTALK TRANSFER matrix INTEGRATED circuits gate array circuits ERRORS MICROELECTRONICS

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If you can't build it, it isn't worth much

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EDN 2004年第7期49卷 49-+页

作者： Moretti, C

The article discusses the design-for-manufacturing, design-for-test, and design-for-yield methods developed by designers and EDA vendors to improve a design's chances for success. One proven way to increase the probability of first-time success in delivering a design is to limit the freedom of designers by using regular and verified structures in manufacturing the die. Synplicity has developed all of its field programmable gate-array (FPGA)-synthesis products in close collaboration with semiconductor vendors and with the involvement of designers. The mode that Synplicity suggests and follows is more flexible, equitable and general. Yield analysis for this class of devices is also more straightforward than what application-specific integrated circuit (ASIC) design requires. Synplicity targets the FPGA market with its Synplify and Synplify Pro logic-synthesis products and with the Amplify physical optimizer to ensure that designs perform correctly once the FPGA is programmed. Most ASIC designers use tools from one of four EDA vendors--Cadence, Magma, Monterey, or Synopsys--to perform synthesis and place-and-route functions. Mentor Graphics supports Design for Manufacturability through its Calibre family of products. Using lithography models and rules, Proteus performs mask synthesis and generates proximity-corrected patterns from the original design patterns. Synopsys has added a verification step after the generation of the mask data with silicon-versus-layout tool.

关键词： Electronic circuit design Lithography Field programmable gate arrays Programmable logic devices gate array circuits

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Configuration errors analysis in SRAM-based FPGAs: Software, tool and practical results

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MICROELECTRONICS RELIABILITY 2007年第9-11期47卷 1836-1840页

作者： Maingot, V. Ferron, J. B. Leveugle, R. Pouget, V. Douin, A. TIMA Lab F-38031 Grenoble France IMS Lab F-33402 Talence France

The reconfigurability of SRAM-based FPGAs has also some drawbacks, especially when used in systems requiring a high level of safety and/or dependability. Dealing with single-event effects is an important issue in these systems. This paper presents a software tool to analyze a bit-stream and the functional effects of errors in it. Results of analyzes are presented, based on experiments using a laser platform to inject faults in the circuit. (C) 2007 Elsevier Ltd. All rights reserved.

关键词： COMPUTER storage devices FIELD programmable gate arrays gate array circuits PROGRAMMABLE logic devices

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Sensing of UO₂²⁺ and Design of Logic gates by the Application of Supramolecular Constructs of Ion-Dependent DNAzymes

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NANO LETTERS 2009年第3期9卷 1196-1200页

作者： Moshe, Michal Elbaz, Johann Willner, Itamar Hebrew Univ Jerusalem Inst Chem Ctr Nanosci & Nanotechnol IL-91904 Jerusalem Israel

Supramolecular constructs composed of ion-dependent DNAzymes and their substrates were used to develop DNAzyme cascades that enabled the sensitive detection Of UO22+ or the activation of logic gate operations. The supramolecular complex between the UO22+-dependent DNAzyme and its substrate leads, in the presence Of UO22+, to the cleavage of the substrate and to the release of the HRP-mimicking DNAzyme that enables the optical analysis Of UO22+ (detection limit 1 x 10(-9) M). Similarly, supramolecular complexes between the Mg2+- and UO22+- dependent DNAzymes and tailored substrates enables the design of the "OR" and "AND" logic gates, using Mg2+ and UO22+ as inputs.

关键词： SUPRAMOLECULAR chemistry CHEMICAL detectors CATALYSTS NUCLEIC acids COMPLEX compounds SCISSION (Chemistry) gate array circuits URANIUM compounds

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MOSFET gate resistance determination

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ELECTRONICS LETTERS 2003年第2期39卷 248-250页

作者： Torres-Torres, R Murphy-Arteaga, RS Decoutere, S Natl Inst Astrophys Opt & Elect INAOE Dept Elect Engn Puebla Mexico IMEC Interuniv Microelect Ctr B-3001 Louvain Belgium

A simple and reliable method to determine a MOSFET's gate resistance (R-in) directly from S-parameter measurements is presented. The extracted data agree well with the data predicted by transmission line theory and show that the main contribution of the transistor's input resistance (R-in) comes from the gate electrode resistance for devices with channel length below 0.2 mum.

关键词： Metal oxide semiconductor field-effect transistors gate array circuits Electric resistance Electric lines

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