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An interpolating time-to-digital converter on an FPGA

INSTRUMENTS AND EXPERIMENTAL TECHNIQUES 2009年第6期52卷 788-792页

作者： Chulkov, V. A. Medvedev, A. V. Penza State Technol Acad Penza 440605 Russia

A simple and sufficiently precise unit converting single time intervals to digital codes on an EP2C20F484C7N Altera field programmable gate array is proposed. The resolution of the converter, the principle of operation of which is based on interpolating the reference period by a great number of outputs of a ring pulse oscillator, is determined by the delay time of the oscillator stage and is 315 ps. The converted interval range is 2.58 A mu s, and the "dead" zone between adjacent conversions does not exceed 5 ns. The circuit does not need any adjustments and is insensitive to supply voltage and environment temperature deviations.

关键词： FIELD programmable gate arrays ELECTRIC oscillators ELECTRIC apparatus & appliances ELECTRIC circuits gate array circuits

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Characterizing universal gate sets via dihedral benchmarking

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Physical Review A 2015年第6期92卷 060302(R)-060302(R)页

作者： Arnaud Carignan-Dugas Joel J. Wallman Joseph Emerson Institute for Quantum Computing and the Department of Applied Mathematics University of Waterloo Waterloo Ontario Canada N2L 3G1 Canadian Institute for Advanced Research Toronto Ontario Canada M5G 1Z8

We describe a practical experimental protocol for robustly characterizing the error rates of non-Clifford gates associated with dihedral groups, including small single-qubit rotations. Our dihedral benchmarking protocol is a generalization of randomized benchmarking that relaxes the usual unitary 2-design condition. Combining this protocol with existing randomized benchmarking schemes enables practical universal gate sets for quantum information processing to be characterized in a way that is robust against state-preparation and measurement errors. In particular, our protocol enables direct benchmarking of the π/8 gate even under the gate-dependent error model that is expected in leading approaches to fault-tolerant quantum computation.

关键词： gate array circuits Dihedral angles (Chemistry) Benchmarking (Management) Quantum theory Qubits

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Topological quantum gate entanglers for a multi-qubit state

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JOURNAL OF PHYSICS A-MATHEMATICAL AND THEORETICAL 2007年第32期40卷 9877-9882页

作者： Heydari, Hoshang Nihon Univ Inst Quantum Sci Chiyoda Ku Tokyo 1018308 Japan

We establish a relation between topological and quantum entanglement for a multi-qubit state by considering the unitary representations of the Artin braid group. We construct topological operators that can entangle a multi-qubit state. In particular we construct operators that create quantum entanglement for multi-qubit states based on the Segre ideal of complex multi-projective space. We also discuss in detail and construct these operators for two-qubit and three-qubit states.

关键词： gate array circuits ENERGY levels (Quantum mechanics) REPRESENTATIONS of algebras OPERATOR theory TOPOLOGICAL spaces

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A High-Resolution Surface Image Capture and Mapping System for Public Roads

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SAE INTERNATIONAL JOURNAL OF PASSENGER CARS-ELECTRONIC AND ELECTRICAL SYSTEMS 2017年第2期10卷 301-309页

作者： Hu, Yazhe Furukawa, Tomonari Virginia Tech Blacksburg VA 24061 USA

This paper presents a system designed to develop a high-resolution map of public roads by capturing high-resolution surface images. Unlike conventional system, the proposed system applies a field programmable gate array (FPGA) to synchronize camera, Inertial Measurement Unit (IMU), and Global Positioning System (GPS) by using FPGA's high clock frequency and flexibility to multiple devices. The proposed system, which can be mounted on a regular vehicle, contains a Complementary Metal-Oxide-Semiconductor (CMOS) camera which can achieve 0.006 ms shutter speed and 150 fps frame rate. This camera's high shutter speed and high frame rate can help capturing images with overlapping region at fast driving speed so that no area is missing from road surface image capturing. The images collected by the proposed system contain clear patterns without motion blur, and feature points on images and feature matching can be found by using existing algorithm like Scale-invariant feature transform (SIFT) between any two consecutive images. Camera's vertical facing towards road surface enables using affine transformation to reduce computational time of registration by calculating only six instead of eight parameters using homography matrix. IMU and GPS data are synchronized and recorded together with image capturing, and is applied to reduce accumulated error for long-distance mapping by providing location information of vehicle for image registration process. A clear map stitched by millimeter-resolution images is obtained at up to 100 km/h and is registered and uploaded to cloud. The road surface mapping can be used in road survey or road maintenance and can visualize public road surface condition. In this paper, the effectiveness of this system and mapping method is illustrated qualitatively and quantitatively through experimental evaluation.

关键词： gate array circuits GLOBAL Positioning System AIR traffic control ARTIFICIAL satellites in navigation SATELLITE-based remote sensing

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Carbon nanotube technology for solid state and vacuum electronics

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IEE PROCEEDINGS-circuits DEVICES AND SYSTEMS 2004年第5期151卷 443-451页

作者： Teo, KBK Lacerda, RG Yang, MH Teh, AS Robinson, LAW Dalal, SH Rupesinghe, NL Chhowalla, M Lee, SB Jefferson, DA Hasko, DG Amaratunga, GAJ Milne, WL Legagneux, P Gangloff, L Minoux, E Schnell, JP Pribat, D Univ Cambridge Cambridge CB2 1PZ England Thales Res & Technol F-91401 Orsay France

The authors demonstrate the fabrication of solid state and vacuum electronic devices using carbon nanotubes as the active channel and emitters. Single wall and multiwall carbon nanotubes (CNT) are deposited directly on substrates using chemical vapour deposition (CVD) and plasma enhanced chemical vapour deposition (PECVD), respectively. The fabrication of top gate and side gate field effect transistors is demonstrated using single wall CNTs. Vertically aligned multiwall CNTs are used to fabricate field emitter arrays or micro-gated field emitters, which have potential application in field emission displays, microwave amplifiers or electron guns.

关键词： NANOTUBES SOLID state electronics VACUUM technology CHEMICAL vapor deposition gate array circuits INTEGRATED circuits

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Tunable THz metamaterials based on an array of paraelectric SrTiO₃ rods

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APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING 2011年第3期103卷 689-692页

作者： Yahiaoui, R. Nemec, H. Kuzel, P. Kadlec, F. Kadlec, C. Mounaix, P. Univ Bordeaux 1 CNRS Lab Ondes & Mat Aquitaine UMR 5798 F-33405 Talence France Acad Sci Czech Republ Inst Phys Prague 18221 8 Czech Republic

This work presents theoretical and experimental investigations of a tunable metamaterial which exhibits negative permeability in the THz frequency range. The tunability is obtained by temperature changes, and the sample consists of an array of high-permittivity SrTiO3 (STO) rods micromachined by a femtosecond laser. Structures exhibiting a negative permeability on multiple frequency bands are also investigated and a proper choice of the dimensions of the pattern allows us to achieve a substantial broadening of the frequency band with negative mu.

关键词： METAMATERIALS PERMEABILITY TITANIUM dioxide MOLECULAR structure gate array circuits MICROELECTROMECHANICAL systems ENERGY bands FEMTOSECOND lasers BARS (Engineering) TEMPERATURE effect

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Quad-level bit-stream adders and multipliers with efficient FPGA implementation

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ELECTRONICS LETTERS 2008年第12期44卷 722-723页

作者： Ng, C. W. Wong, N. Ng, T. S. Univ Hong Kong Dept Elect & Elect Engn Hong Kong Hong Kong Peoples R China

Novel adder and multiplier circuits for bit-stream signal processing customised for quad-level sigma-delta modulated signals are proposed. Compared with existing sorter-based quad-level sigma-delta adders and multipliers, the proposed implementation is more resource-efficient (> 76% hardware savings) and faster (> 93% higher clock frequency) when realised on state-of-the-art FPGA architecture featuring six-input look-up tables.

关键词： Signal processing Information measurement Field programmable gate arrays gate array circuits Programmable logic devices Logic devices

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The impact of interface/border defect on performance and reliability of high-k/metal-gate CMOSFET

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MICROELECTRONICS RELIABILITY 2013年第2期53卷 265-269页

作者： Yeh, Wen-Kuan Chen, Po-Ying Gan, Kwang-Jow Wang, Jer-Chyi Lai, Chao Sung Natl Univ Kaohsiung Dept Elect Engn Kaohsiung Taiwan I Shou Univ Dept Informat Engn Kaohsiung Taiwan Natl Chiayi Univ Dept Elect Engn Chiayi Taiwan Chang Gung Univ Dept Elect Engn Tao Yuan Taiwan

The impact of interface/border defect on performance and reliability was investigated for gate-first and gate-last high-k/metal-gate CMOSFET. For high-k/metal-gate CMOSFET, V-FB roll-off is critical as effective oxide thickness (EOT) scales below 15 angstrom (angstrom) especially for metal gate-first device with an extra capping layer to adjust V-TH. By proposing a model of metal-gate process induced interface trap releasing oxygen, the vertical and lateral interface trap distribution and the dependence of interfacial layer (IL) on V-FB roll-off phenomena can be well interpreted. In this work, we found that V-FB roll-off can be improved by reducing oxygen vacancy (V-O) at the HfO2/IL interface with suppression of oxygen diffusion from high-k to IL By the way, a metal gate-last process with lower interface trap was proposed to minimize V-O formation by suppress oxygen releasing, thus optimize a 28 nm 15 angstrom EOT HfO2/metal-gate CMOSFET with low V-FB-EOT roll-off, it can be a reference for sub 22 nm CMOSFET with thin EOT (<15 angstrom) design. (C) 2012 Elsevier Ltd. All rights reserved.

关键词： SEMICONDUCTOR junctions RELIABILITY (Engineering) METAL oxide semiconductor field-effect transistors -- Performance OXYGEN DIFFUSION gate array circuits

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Improved high-field reliability for a SiC metal-oxide-semiconductor device by the incorporation of nitrogen into its HfTiO gate dielectric

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JOURNAL OF APPLIED PHYSICS 2007年第5期102卷 054515.1-054515.5页

作者： Lin, L. M. Lai, P. T. Univ Hong Kong Dept Elect & Elect Engn Hong Kong Hong Kong Peoples R China

Materials with high dielectric constant (k) have been used in SiC-based metal-oxide-semiconductor (MOS) devices to reduce the electric field in the gate dielectric and thus suppress a high-field reliability problem. In this work, high-k gate dielectrics HfxTi1-xO2 and HfxTi1-xON are applied in SiC MOS devices and an ultrathin thermally grown SiO2 is used as an interlayer between SiC and the high-k materials to block electron injection from SiC into the low-barrier high-k materials. Incorporating nitrogen into the Hf-Ti oxide (by adding nitrogen gas during its sputtering) stacked with a SiO2 interlayer (HfxTi1-xO/SiO2) results in a better gate dielectric for the MOS capacitor, such as smaller frequency dispersion in the capacitance-voltage curve, less oxide charges, and better interface quality. Moreover, the nitrogen incorporation increases the dielectric constant of the oxide, but causes higher dielectric leakage, which can be suppressed by the SiO2 interlayer. High-field stress under constant electric field is performed on the stacked/nonstacked Hf-Ti oxides and oxynitrides, and it turns out that the two oxynitrides show a much smaller flatband shift and a less stress-induced leakage current compared with the two oxides. Based on these results, the HfxTi1-xON/SiO2 stack could be a promising high-k gate dielectric for SiC MOS devices with enhanced reliability. (c) 2007 American Institute of Physics.

关键词： METAL oxide semiconductors ELECTROMAGNETIC fields DIELECTRIC devices gate array circuits THIN films

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One-way gates based on EPR, GHZ and decoherence-free states of W class

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PHYSICS LETTERS A 2009年第38期373卷 3410-3412页

作者： Basharov, A. M. Gorbachev, V. N. Trubilko, A. I. Yakovleva, E. S. Kurchatov Inst Lab Nonlinear Opt Moscow Russia

The logical gates using quantum measurement as a primitive of quantum computation are considered. It is found that these gates achieved with EPR, GHZ and W entangled states have the same structure, allow encoding the classical information into states of quantum system and can perform any calculations. A particular case of decoherence-free W states is discussed as in this very case the logical gate is decoherence-free. (C) 2009 Elsevier B.V. All rights reserved.

关键词： COHERENT states gate array circuits SYMBOLIC & mathematical logic QUANTUM theory ENERGY levels (Quantum mechanics) ELECTRON paramagnetic resonance

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