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Non-Volatile Threshold Adaptive Transistors with Embedded RRAM

Chinese Physics Letters 2014年第10期31卷 153-156页

作者：邓宁贾弘扬吴畏吴华强 Institute of Microelectronics Tsinghua University Beijing 100084

We propose a novel nonvolatile threshold adaptive transistor （TAT） for neuromorphic circuits. The threshold adaptive transistor is achieved by embedding a resistive random-access memory （RRAM） material stack between the gate electrode and gate dielectric. During operation, the embedded RRAM device is kept at a high resistance state, which makes it act as a nonvolatile capacitor. The threshold could be nonlinearly adjusted by the voltage pulses applied on the gate of the transistor. We quantitatively estimate the range of the capacitance variation of the RRAM device. The threshold voltage of the TAT is simulated and shows expected variation. The simulated output of an inverter using a TAT shows a nonlinear adaptive behavior.

关键词： TRANSISTORS NONVOLATILE random-access memory THRESHOLD voltage EMBEDDING theorems gate array circuits

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Low-power fast-update pipelined phase accumulator for CML-based high-speed CMOS DDFSs

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ELECTRONICS LETTERS 2012年第18期48卷 1102-1103页

作者： Yoo, T. Cho, S. -J. Lee, J. W. Baek, K. -H. Chung Ang Univ Sch Elect & Elect Engn Seoul 156756 South Korea

Presented is a phase accumulator (PACC) for current-mode logic (CML)-based high-speed CMOS direct digital frequency synthesisers (DDFSs). The proposed PACC not only consumes low power by using an adaptive power reduction technique, but also updates frequency information within one clock period by using dual function logic gates and the charge sharing scheme that accelerates current recovery time. This work reduces power consumption by 33% compared to the conventional PACC with a pipeline depth of 8 and 32-bit FCW.

关键词： STORAGE batteries LOW voltage integrated circuits COMPLEMENTARY metal oxide semiconductors FREQUENCY synthesizers gate array circuits

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Improving 90nm FPGA chips with an alternating phase-shift mask

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MICROLITHOGRAPHY WORLD 2006年第4期15卷 12-15页

作者： Ho, Jonathan Chacko, Manoj Panaite, Petrisor Xilinx Inc Next Generat Prod Dev San Jose CA USA Synopsys Inc Mask Synth Tools Mountain View CA 94043 USA

The article discusses how to improve nonphase-compliant 90 nanometer field-programmable gate arrays (FPGA) using dark field, double exposure alternating phase-shift gate mask (Alt-PSM). The FPGA yield and performance are improved by reducing its width and line-end shortening. Implementing the Alt-PSM in production has been challenging due to phase conflict errors, mask manufacturing difficulties, and the increased production cost of the two mask exposures.

关键词： FIELD programmable gate arrays NANOSTRUCTURED materials gate array circuits PROGRAMMABLE logic devices ELECTRONIC circuits

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Investigation on the thermal behavior of 0.15 μm gate-length In_0.4Al_0.6As/In_0.4Ga_0.6As MHEMT

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MICROELECTRONICS RELIABILITY 2012年第6期52卷 969-973页

作者： Lin, Che-Kai Chiu, Hsien-Chin Lin, Chao-Wei Kao, Hsuan-ling Chien, Feng-Tso Chang Gung Univ Dept Elect Engn Tao Yuan Taiwan Feng Chia Univ Dept Elect Engn Taichung 40724 Taiwan

In this study, we have successfully investigated the electrical performances of In0.4Al0.6As/In0.4Ga0.6As metamorphic high-electron-mobility transistor (MHEMT) at temperatures range from 275 K to 500 K comprehensively. By extracting the device S-parameters, the temperature dependent small signal model has been established. At room temperature, 0.15 mu m T-gate device with double delta-doping design exhibits f(T) and f(MAX) values of 103 GHz and 204 GHz at V-ds = 1 V, an extrinsic transconductance of 678 mS/mm, and a current density of 578 mA/mm associated with a high breakdown voltage of -13 V. Power measurements were evaluated at 40 GHz and the measured output power, linear power gain, and maximum power-added efficiency, were 7.12 dBm, 10.15 dB, and 23.1%, respectively. The activation energy (E-a) extracted from Arrhenius plots is = 0.34 eV at 150 <= T <= 350 K. The proposed device is promisingly suitable for millimeter-wave power application. (C) 2012 Elsevier Ltd. All rights reserved.

关键词： THERMAL analysis gate array circuits GALLIUM arsenide MODULATION-doped field-effect transistors TEMPERATURE effect ACTIVATION energy ARRHENIUS equation

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Domino inspired MOBILE networks

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ELECTRONICS LETTERS 2012年第5期48卷 292-U1596页

作者： Nunez, J. Avedillo, M. J. Quintana, J. M. Univ Seville IMSE CNM CSIC Inst Microelect Sevilla Seville Spain

MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly chained, a four-phase clock scheme is required. A single phase scheme has been recently reported that alternates rising and falling edge-triggered MOBILE gates. A novel two-phase interconnection scheme resembling conventional domino pipelines is proposed and validated. It exhibits advantages in terms of speed with respect to both four-phase and single-phase interconnection schemes. In addition, the new architecture improves logic flexibility regarding the domino pipeline counterpart, since inverting and non-inverting stages can be interspersed.

关键词： Tunnel diodes Interconnects (Integrated circuit technology) Quantum electronics Electric networks gate array circuits

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Modelling of the shoot-through phenomenon introduced by the next generation IGBT in inverter applications

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MICROELECTRONICS RELIABILITY 2017年第Sep.期76卷 465-469页

作者： Abe, S. Hasegawa, K. Tsukuda, M. Wada, K. Omura, I. Ninomiya, T. Kyushu Inst Technol Dept Life Sci & Syst Engn Kitakyushu Fukuoka Japan Green Elect Res Inst Kitakyushu Fukuoka Japan Tokyo Metropolitan Univ Dept Elect & Elect Engn Tokyo Japan

The shoot-through phenomenon has not been fully discussed for high-power inverters with IGBTs. This is because a negative gate voltage is applied to IGBTs during off states. Recently, attention is paid to an improved gate driver with only a positive gate voltage in order to meet demands for simplification, integration, and reduction in power consumption as well as in cost of the gate driver. Moreover, the threshold voltage of the next-generation IGBT will decrease with microfabrication techniques of the gate structure. This will make the shoot through phenomenon severer and degrade the inverter reliability with the next-generation IGBTs. The influence of the parasitic parameters in both the IGBT and circuit on the shoot-through mechanism has not been investigated so far. This paper clarifies the shoot-through mechanism and investigates the impact of the next generation IGBTs on the inverter reliability. The influence of the internal capacitance of IGBT including stray inductance on inverter reliability is experimentally confirmed. (C) 2017 Elsevier Ltd. All rights reserved.

关键词： INSULATED gate bipolar transistors THRESHOLD voltage ELECTRIC inverters ELECTRIC power consumption gate array circuits RELIABILITY of electronics

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Simulation and modelling of VDMOSFET self protection under TLP-stress

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MICROELECTRONICS RELIABILITY 2010年第2期50卷 183-189页

作者： Sauter, Martin Willemen, Joost Univ Fed Armed Forces Dept Elect Engn & Comp Sci D-85577 Neubiberg Germany Infineon Technol Business Unit Automot Power Semicond D-85579 Neubiberg Germany

We present a simple and practical model for modelling the electrical behaviour of scalable vertical diffused MOSFETs (VDMOSFETs) under TLP stress. The trigger current is found to be dependent from gate-source voltage and geometry. A scalable model for analog circuit simulation is developed. As application example, self protection of VDMOS in resistive coupled gate configuration is investigated. For this purpose the device behaviour under TLP stress is modelled. The model is shown to predict VDMOS self protection under TLP stress for a wide range of geometries in an excellent way. A comprehensive analytical model Calculation is added which explains the range of model validity. Within this range maximum HBM rating of the resistive gate coupled devices is predicted correctly. (C) 2009 Elsevier Ltd. All rights reserved.

关键词： SIMULATION methods & models METAL oxide semiconductor field-effect transistors ELECTRIC lines STRAINS & stresses (Mechanics) gate array circuits METAL oxide semiconductors

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Field programmable gate array prototyping of end-around carry parallel prefix tree architectures

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IET COMPUTERS AND DIGITAL TECHNIQUES 2010年第4期4卷 306-316页

作者： Liu, F. Tan, Q. Chen, G. Song, X. Mohamed, O. Ait Gu, M. Lingcore Lab Portland OR USA Portland State Univ ECE Dept Portland OR 97207 USA Concordia Univ ECE Dept Montreal PQ Canada Tsinghua Univ Sch Software Beijing 100084 Peoples R China

As an important part of many processors's floating point unit, fused multiply-add unit performs a multiplication followed immediately by an addition. In IBM POWER6 microprocessor's fused multiply-add unit, a fast 128-bit floating-point end-around-carry (EAC) adder is proposed. Very few algorithmic details exist in today's literature about this adder. In this study, a complete designed EAC adder that can work independently as a regular adder is proposed. Details about the proposed EAC adder's arithmetic algorithms are described. In IBM's original EAC adder, the Kogge-Stone tree has been chosen for its high performance on ASIC technology. In this study, the authors present a comparative study on different parallel prefix trees which are used in the design of our new EAC adder targeting field programmable gate array (FPGA) technology. Our study highlights the main performance differences among 14 different architecture configurations focusing on the area requirements and the critical path delay. The experimental results show that there is one architecture configuration with the lower area requirement and the higher performance.

关键词： FIELD programmable gate arrays PROGRAMMABLE logic devices gate array circuits MICROPROCESSORS ALGORITHMS

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Quantum interference through gated single-molecule junctions

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CHEMICAL PHYSICS LETTERS 2012年 530卷 86-92页

作者： Lovey, Daniel A. Romero, Rodolfo H. Univ Nacl Nordeste Fac Ciencias Exactas & Nat & Agrimensura RA-3400 Corrientes Argentina Consejo Nacl Invest Cient & Tecn Inst Modelado & Innovac Tecnol RA-3400 Corrientes Argentina

We discuss the general form of the transmission spectrum through a molecular junction in terms of the Green function of the isolated molecule. By introducing a tight binding method, we are able to translate the Green function properties into practical graphical rules for assessing beforehand the possible existence of antiresonances in an energy range for a given choice of connecting sites. The analysis is exemplified with a benzene molecule under a hypothetical local gate, which allows one to continuously tune the on-site energy of single atoms, for various connection topologies and gate positions. (C) 2012 Elsevier B. V. All rights reserved.

关键词： QUANTUM interference GREEN'S functions MOLECULAR electronics SPECTRUM analysis gate array circuits BENZENE SOLID state physics

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DC pulse hot-carrier-stress effects on gate-induced drain leakage current in n-channel MOSFETs

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2001年第12期48卷 2746-2753页

作者： Chen, JH Wong, SC Wang, YH Natl Cheng Kung Univ Dept Elect Engn Tainan 70101 Taiwan Taiwan Semicond Mfg Co Hsinchu 300 Taiwan

The dc pulse hot-carrier-stress effects on the degradation in gate-induced drain leakage (GIDL) current in a high field regime and the mechanisms of stress-induced degradation are studied. In this paper, we investigate de pulse stress parameters in GIDL which include frequency, rise/fall time, and amplitude of stressing pulse. The contribution of hot-hole injection, interface state generation, and hot-electron injection in a period of transient stress are identified. It is found that the device degradation increases with increased pulse frequency under maximum gate current stress, while it decreases with reduced pulse frequency under maximum substrate current stress. This work is useful for de pulse hot-carrier-stress reliability analysis under circuit operation.

关键词： HOT carriers gate array circuits SCIENTIFIC experimentation

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