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Field programmable gate array prototyping of end-around carry parallel prefix tree architectures

IET COMPUTERS AND DIGITAL TECHNIQUES 2010年第4期4卷 306-316页

作者： Liu, F. Tan, Q. Chen, G. Song, X. Mohamed, O. Ait Gu, M. Lingcore Lab Portland OR USA Portland State Univ ECE Dept Portland OR 97207 USA Concordia Univ ECE Dept Montreal PQ Canada Tsinghua Univ Sch Software Beijing 100084 Peoples R China

As an important part of many processors's floating point unit, fused multiply-add unit performs a multiplication followed immediately by an addition. In IBM POWER6 microprocessor's fused multiply-add unit, a fast 128-bit floating-point end-around-carry (EAC) adder is proposed. Very few algorithmic details exist in today's literature about this adder. In this study, a complete designed EAC adder that can work independently as a regular adder is proposed. Details about the proposed EAC adder's arithmetic algorithms are described. In IBM's original EAC adder, the Kogge-Stone tree has been chosen for its high performance on ASIC technology. In this study, the authors present a comparative study on different parallel prefix trees which are used in the design of our new EAC adder targeting field programmable gate array (FPGA) technology. Our study highlights the main performance differences among 14 different architecture configurations focusing on the area requirements and the critical path delay. The experimental results show that there is one architecture configuration with the lower area requirement and the higher performance.

关键词： FIELD programmable gate arrays PROGRAMMABLE logic devices gate array circuits MICROPROCESSORS ALGORITHMS

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Nonvolatile Memory Effect in Organic Thin-Film Transistor Based on Aluminum Nanoparticle Floating gate

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Chinese Physics Letters 2010年第1期27卷 275-278页

作者：王伟马东阁 State Key Laboratory of Polymer Physics and Chemistry Changchun Institute of Applied Chemistry Chinese Academy of Sciences Changchun 130022 State Key Laboratory of Integrated Optoelectronics College of Electronic Science and Engineering Jilin University Changchun 130012 Graduate School of Chinese Academy of Sciences Beijing 100049

A nonvolatile memory effect was observed in an organic thin-film transistor by introducing a floating gate structure. The floating gate was composed of an Al film in a thickness of nanometers, which was thermally deposited on a SiO2 insulator and exposed to air to spontaneously oxidize. It can be seen that the transistors exhibit significant hysteresis behaviors and storage circles in current-voltage characteristics in the dark and under illumination, indicating that the transistors may act as a nonvolatile memory element. The operational mechanism is discussed in the cases of dark and illumination via charge trapping by the Al floating gate.

关键词： THIN film transistors ORGANIC thin films FERROELECTRIC storage cells NANOPARTICLES ALUMINUM gate array circuits ELECTRIC insulators & insulation

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Improvement of TDDB reliability, characteristics of HfO₂ high-k/metal gate MOSFET device with oxygen post deposition annealing

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MICROELECTRONICS RELIABILITY 2010年第5期50卷 618-621页

作者： Hsu, Chia-Wei Fang, Yean-Kuen Yeh, Wen-Kuan Chen, Chun-Yu Chiang, Yen-Ting Juang, Feng-Renn Lin, Chien-Ting Lai, Chien-Ming Natl Cheng Kung Univ Dept Elect Engn Inst Microelect VLSI Technol Lab Tainan 701 Taiwan Natl Univ Kaohsiung Dept Elect Engn Kaohsiung Taiwan UMC Cent R&D Div Hsinchu 300 Taiwan

In this work, influences of oxygen effect on an Hf-based high-k gate dielectric were investigated. A post deposition annealing (PDA) including oxygen ion after high-k dielectric deposition was used to improve reliability of the Hf-based high-k/metal gate device. The basic electrical characteristics of devices were compared with and without the PDA process. Experiment results show that the oxygen PDA did not degrade the drive current and effective oxide thickness of the Hf-based gate devices. In addition, reliability issues such as positive bias instability, negative bias instability and TDDB were also improved by the oxygen PDA significantly. During the TDDB test, the charge trapping was characterized by an in situ charge pumping system, which could make us to understand the variations of interface trap during the reliability stress easily. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： BREAKDOWN (Electricity) RELIABILITY (Engineering) HAFNIUM oxide gate array circuits OXYGEN ANNEALING of metals MICROELECTRONICS INTERFACES (Physical sciences)

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Device and circuit level suppression techniques for random-dopant-induced static noise margin fluctuation in 16-nm-gate SRAM cell

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MICROELECTRONICS RELIABILITY 2010年第5期50卷 647-651页

作者： Lee, Kuo-Fu Li, Yiming Li, Tien-Yen Su, Zhong-Cheng Hwang, Chin-Hong Natl Chiao Tung Univ Dept Elect Engn Hsinchu 300 Taiwan Natl Chiao Tung Univ Inst Commun Engn Hsinchu 300 Taiwan Natl Nano Device Labs Hsinchu 300 Taiwan

In this study, a three-dimensional "atomistic" coupled device-circuit simulation is performed to explore the impact of process-variation-effect (PVE) and random-dopant-fluctuation (RDF) on static noise margin (SNM) of 16-nm complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) cells. Fluctuation suppression approaches, based on circuit and device viewpoints, are further implemented to examine the associated characteristics in 16-nm-gate SRAM cells. From the circuit viewpoint, the SNM of 8T planar SRAM is enlarged to 230 mV and the variation of SNM (sigma(SNM)) is reduced to 22 mV at a cost of 30% extra chip area. As for device level improvement, silicon-on-insulator (SOI) FinFETs replaced the planar MOSFETs in 6T SRAM is further examined. The SNM of 6T SOI FinFETs SRAM is 125 mV and the sigma(SNM) is suppressed significantly to 5.4 mV. However, development of fabrication process for SOI FinFET SRAM is crucial for sub-22 nm technology era. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： ELECTRIC circuits ELECTRONIC noise FLUCTUATIONS (Physics) RANDOM access memory gate array circuits CHARGE coupled devices SIMULATION methods & models COMPLEMENTARY metal oxide semiconductors METAL oxide semiconductor field-effect transistors

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Discrete Charge Storage Nonvolatile Memory Based on Si Nanocrystals with Nitridation Treatment

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Chinese Physics Letters 2010年第8期27卷 180-182页

作者：张贤高陈坤基方忠慧钱昕晔刘广元江小帆马忠元徐骏黄信凡计建新何飞宋矿宝张俊万辉王荣华 National Laboratory of Solid State Microstructures and Department of Physics Nanjing University Nanjing 210093 Wuxi China Resources Huajing Micro Electronics Co. Ltd. Wuxi 214061

A nonvolatile memory device with nitrided Si nanocrystals embedded in a floating gate was fabricated. The uniform Si nanocrystals with high density （3× 10^11 cm^-2 ） were deposited on ultra-thin tunnel oxide layer （- 3 nm） and followed by a nitridation treatment in ammonia to form a thin silicon nitride layer on the surface of nanocrystals. A memory window of 2.4 V was obtained and it would be larger than 1.3 V after ten years from the extrapolated retention data. The results can be explained by the nitrogen passivation of the surface traps of Si nanoerystals, which slows the charge loss rate.

关键词： COMPUTER storage devices ELECTRIC charge & distribution SILICON crystals NANOCRYSTALS NITRIDING gate array circuits DENSITY AMMONIA

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Analysis of dependence of short-channel effects in double-gate MOSFETs on channel thickness

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MICROELECTRONICS RELIABILITY 2010年第3期50卷 332-337页

作者： Kobayashi, Yusuke Kakushima, Kuniyuki Ahmet, Parhat Rao, V. Ramgopal Tsutsui, Kazuo Iwai, Hiroshi Tokyo Inst Technol Dept Elect & Appl Phys Midori Ku Kanagawa 2268502 Japan Tokyo Inst Technol Frontier Collaborat Res Ctr Midori Ku Kanagawa 2268502 Japan Indian Inst Technol Dept Elect Engn Bombay 400076 Maharashtra India

A systematic study of the dependence of short-channel effects (SCEs) on the channel thickness (Tch) of double-gate MOSFETs revealed that there is a particular range of Tch in which SCEs are significantly degraded compared to those of conventional planar MOSFETs. This phenomenon was found to originate from the electric field penetrating the channel region from the drain due to the disappearance of a neutral region in the channel. This dependence of this phenomenon on device parameters such as the channel doping concentration (Nc), the equivalent oxide thickness (EOT) and the gate length (Lg) was examined. The degradation of SCEs due to an inappropriate Tch was found to become more significant as Nc and Lg are reduced. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： METAL oxide semiconductor field-effect transistors gate array circuits ELECTRIC fields ELECTRONIC apparatus & appliances INTEGRATED circuits

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Quantum circuit's reliability assessment with VHDL-based simulated fault injection

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MICROELECTRONICS RELIABILITY 2010年第2期50卷 304-311页

作者： Boncalo, Oana Amaricai, Alexandru Udrescu, Mihai Vladutiu, Mircea Politehn Univ Timisoara Dept Comp Sci & Engn Timisoara Romania

This paper presents a VHDL-based simulated fault injection (SFI) methodology for quantum circuits. The main objective is to attain a high error modeling capability at a technology independent level. For this purpose, gate level simulation models for quantum circuits have been developed using VHDL The proposed methodology relies on specific techniques inspired from the simulated fault injection techniques developed for classical CMOS circuits: saboteurs and mutants. In order to perform the simulation campaigns, a library of quantum gates and simulated fault injection components has been developed. The simulation results show that a wide range of quantum faults and error models has been addressed. Furthermore, a comparison between the two SFI techniques is presented. (C) 2009 Elsevier Ltd. All rights reserved.

关键词： QUANTUM communication INTEGRATED circuits RELIABILITY (Engineering) VHDL (Computer hardware description language) SIMULATION methods & models MEASUREMENT errors gate array circuits COMPLEMENTARY metal oxide semiconductors

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Effects of oxygen content and postdeposition annealing on the physical and electrical properties of thin Sm₂O₃ gate dielectrics

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APPLIED SURFACE SCIENCE 2010年第23期256卷 7186-7193页

作者： Pan, Tung-Ming Huang, Chun-Chin Chang Gung Univ Dept Elect Engn Tao Yuan 333 Taiwan

In this paper, we describe the physical properties and electrical characteristics of thin Sm2O3 dielectric films deposited on Si (100) by means of rf reactive sputtering. The structural and morphological features of these films were studied, as a function of the growth conditions (three various argon-to-oxygen flow ratios: 10/15, 15/10 and 20/5, and temperature from 600 to 800 degrees C), by x-ray diffraction, atomic force microscopy, and x-ray photoelectron spectroscopy. It is found that Sm2O3 dielectric prepared under 15/10 flow ratio and annealed at 700 degrees C exhibits a thinner capacitance equivalent thickness and excellent electrical properties, including the interface trap density, the hysteresis and frequency dispersion in the capacitance-voltage curves. This condition is attributed to the reduction of the interfacial SiO2 and silicate formation, and the small of surface roughness due to the optimization of oxygen in the Sm2O3 film. (C) 2010 Elsevier B.V. All rights reserved.

关键词： THIN films -- Electric properties METALLIC oxides SAMARIUM ANNEALING of metals gate array circuits SPUTTERING (Physics) TEMPERATURE effect INTERFACES (Physical sciences)

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Modeling of drain current, capacitance and transconductance in thin film undoped symmetric DG MOSFETs including quantum effects

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MICROELECTRONICS RELIABILITY 2010年第3期50卷 338-345页

作者： Mohammadi, Saeed Afzali-Kusha, Ali Univ Tehran Nanoelect Ctr Excellence Sch Elect & Comp Engn Tehran Iran

In this paper, we present a fast yet accurate semi-analytical model for the I-V and C-V characteristics of nanoscale undoped symmetric double gate (DG) MOSFETs. The model employs a parabolic potential approximation for the body potential in the coordinate normal to the interfaces in all regions of device operation. While carrier confinement phenomenon is taken into account, we calculate the surface electric field which is used to determine the inversion charge sheet density. The density is used in a compact classical model of the symmetric DG MOSFET as a core model. Some quantum effects which include the threshold voltage shift and effective oxide thickness increment are applied through some modifications to the core model. To assess the accuracy of the proposed model, the results of the model are compared to those of the numerical simulations. The comparison reveals the high accuracy of the proposed model. (C) 2009 Elsevier Ltd. All rights reserved.

关键词： METAL oxide semiconductor field-effect transistors SEMICONDUCTOR films NANOSTRUCTURED materials gate array circuits INTERFACES (Physical sciences) ELECTRIC fields NUMERICAL analysis SIMULATION methods & models

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ESD protection for thin gate oxides in 65 nm

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MICROELECTRONICS RELIABILITY 2010年第1期50卷 26-31页

作者： Notermans, Guido Smedes, Theo Mrcarica, Zeljko de Jong, Peter Stephan, Ralph van Zwol, Hans Maksimovic, Dejan ST Ericsson CH-8045 Zurich Switzerland NXP Semicond NL-6535 AE Nijmegen Netherlands

Unexpected functional failures were found in the core of an IC, processed in a 65 nm technology with 1.8 nm gate oxide, after Machine Model (MM) testing, although a comprehensive rail-based protection scheme was applied. Failure analysis was performed including Obirch, backside de-processing, and SEM analysis to locate the failure in the gate oxide of several core NMOS transistors. Careful Transmission Line Pulse (TLP) measurements on NMOSTs with 1.8 nm oxides yields a mean BVox = 6.06 V and standard deviation of 0.18 V, after correction for MM test conditions. Comparison with a mean Vt1 = 5.35 V and a standard deviation of 0.15 V for ggNMOSTs shows that the tails of the BVox and Vt1 distributions overlap. This implies that connecting a gate to a drain diffusion does not guarantee adequate protection for a 1.8 nm gate oxide in a 65 nm technology. (C) 2009 Elsevier Ltd. All rights reserved.

关键词： ELECTRIC discharges gate array circuits FAILURE analysis (Engineering) INTEGRATED circuits SCANNING electron microscopy METAL oxide semiconductor field-effect transistors ELECTRIC lines STANDARD deviations

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