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Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware

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IET COMPUTERS AND DIGITAL TECHNIQUES 2008年第5期2卷 386-400页

作者： Wang, J. Chen, Q. S. Lee, C. H. Inha Univ Dept Informat & Commun Engn Inchon South Korea

The authors present a novel virtual reconfigurable architecture (VRA) for realising real-world applications of intrinsic evolvable hardware (EHW) on field programmable gate arrays (FPGAs). The phenotype representation of the proposed evolvable system is based on a two-dimensional function element (FE) network. Compared with the traditional Cartesian genetic programming, the proposed approach includes more connection restrictions in the FE network to reduce genotype length. Another innovative feature of the VRA is that the whole evolvable system, which consists of an evolutionary algorithm unit, a fitness value calculation unit and an FE array unit, can be realised on a single FPGA. On this work, a custom Xilinx Virtex xcv2000E FPGA, which is fitted in the Celoxica RC1000 Peripheral Component Interconnect (PCI) board is utilised as the hardware platform. The main motive of the research is to design a general, flexible evolvable system with powerful computation ability to achieve intrinsic evolution. As examples, the proposed evolvable system is devoted to evolve two real-world applications: a character recogniser and an image operator by using gate level evolution and function level evolution, respectively. The experimental results show that the VRA can bring higher computational ability and more fiexibility than traditional approach to intrinsic EHW.

关键词： COMPUTER input-output equipment FIELD programmable gate arrays gate array circuits PCI bus (Computer bus) DIGITAL technology

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FPGA implementation of multiplication-free complex division

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ELECTRONICS LETTERS 2008年第2期44卷 95-97页

作者： Liu, J. Weaver, B. Zakharov, Y. Univ York Dept Elect Commun Res Grp York YO10 5DD N Yorkshire England

The FPGA implementation of a new complex division algorithm is described. It is based on the dichotomous co-ordinate descent method and requires only bit-shift and addition operations. Consequently, the footprint of t... 详细信息

关键词： gate array circuits Digital signal processing Semiconductors Electrical engineering Electronics research

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A novel approach to characterization of progressive breakdown in high-k/metal gate stacks

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MICROELECTRONICS RELIABILITY 2008年第11-12期48卷 1759-1764页

作者： Pagano, R. Lombardo, S. Palumbo, F. Kirsch, P. Krishnan, S. A. Young, C. Choi, R. Bersuker, G. Stathis, J. H. CNR IMM I-95121 Catania Italy CNEA CONICET Buenos Aires DF Argentina SEMATECH Austin TX 78741 USA IBM Res Div Yorktown Hts NY 10598 USA

Dielectric breakdown (BD) of nFETs with TiN metal gates and HfO2/interfacial layer with 1.09 nm EOT is studied. Occurrence of progressive BD at low current levels is demonstrated. A new measurement methodology for extraction of the PBD time and its dependence on gate voltage are reported. (C) 2008 Elsevier Ltd. All rights reserved.

关键词： BREAKDOWN (Electricity) gate array circuits DIELECTRICS HAFNIUM oxide ELECTRIC currents MICROELECTRONICS

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An automated approach for locating multiple faulty LUTs in an FPGA

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MICROELECTRONICS RELIABILITY 2008年第11-12期48卷 1900-1906页

作者： Kumar, T. Nandha Chong, Chia Wai Univ Nottingham Fac Engn Semenyih 43500 Selangor Malaysia

This paper presents a new approach for locating any multiple faulty look-up tables (LUTs) in a field programmable gate array (FPGA). This is a high resolution approach, in which the position of each of the multiple faulty LUTs is precisely determined without any fault masking. To identify the fault location, a new technique is used by correlating the position of each of the LUT to a particular select signal of a dedicated wide input multiplexer along with a control logic. This off-line built in self test (BIST) method can be invoked automatically whenever the testing is required to be carried out. The total testing time of the LUTs under test for different configurations have been reduced to a greater extend as the reconfiguration is performed at the physical circuit description level rather than at the high level abstract. It is shown that average reconfiguration duration is approximately 30 s for Spartan series FPGAs. Also, it is shown that the total testing time required to test 9312 LUTs exhaustively per configuration is 2 min and 4 s. Thus, it is possible to exhaustively test LUTs with multiple configurations in a shorter span of time. Moreover, this approach uses minimal IOBs and provides 100% logic fault coverage. This approach is tested on Xilinx Spartan family FPGAs, and results are provided. (C) 2008 Elsevier Ltd. All rights reserved.

关键词： FIELD programmable gate arrays FAULT location (Engineering) CONFIGURATIONS (Geometry) gate array circuits DYNAMIC testing TEST systems

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Implementing FFT-Based Digital Channelized Receivers on FPGA Platforms

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IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS 2008年第4期44卷 1567-1585页

作者： Sanchez, Miguel A. Garrido, Mario Lopez-Vallejo, Marisa Grajal, Jesus Univ Politecn Madrid ETSI Telecomunicac Dept Ingn Elect E-28040 Madrid Spain Univ Politecn Madrid ETSI Telecomunicac Dept Senales Sistemas & Radiocomunicac E-28040 Madrid Spain

This paper presents an in-depth study of the implementation and characterization of fast Fourier transform (FFT) pipelined architectures suitable for broadband digital channelized receivers. When Implementing the FFT algorithm on field-programmable gate array (FPGA) platforms, the primary goal is to maximize throughput and minimize area. Feedback and feedforward architectures have been analyzed regarding key design parameters: radix, bitwidth, number of points and stage scaling. Moreover, a simplification of the FFT algorithm, the monobit FFT, has been implemented in order to achieve faster real time performance in broadband digital receivers. The influence of the hardware implementation on the performance of digital channelized receivers has been analyzed In depth, revealing interesting Implementation trade-offs which should be taken into account when designing this kind of signal processing systems on FPGA platforms.

关键词： ALGORITHMS FOURIER transforms gate array circuits SIGNAL processing DIGITAL electronics PIPELINING (Electronics)

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Error propagation analysis using FPGA-based SEU-fault injection

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MICROELECTRONICS RELIABILITY 2008年第2期48卷 319-328页

作者： Ejlall, Allreza Miremadi, Seyed Ghassem Sharif Univ Technol Dept Comp Engn Tehran Iran

Error propagation analysis is one of the main objectives of fault injection experiments. This analysis helps designers to detect design mistakes and to provide effective mechanisms for fault tolerant systems. However, error propagation analysis requires that the chosen fault injection technique provides a high degree of observability (i.e., the ability to observe the internal values and events of a circuit after a fault is injected). Simulation-based fault injection provides a high observability adequate for error propagation analysis. However, the performance of the simulation-based technique is inadequate to handle today's hardware complexity. As an alternative, FPGA-based fault injection can be used to accelerate the fault injection experiments, but the communication time needed for observing the circuit behavior from outside of the FPGA imposes severe limitations on the observability. In this paper, an observation technique for FPGA-based fault injection is proposed which significantly reduces the communication time as compared with previous scan-based observation techniques. Furthermore, this paper describes a SEU-fault injection technique based on a chain of parallel registers which reduces the time needed for injecting SEU faults as compared to the previous scan-based fault-injection techniques. As a case study, a 32-bit pipelined processor has been used in the fault injection experiments. The experimental results show that when a high degree of observability is required (e.g., error propagation analysis), the proposed fault injection technique is over 1166 times faster than simulation-based fault injection, whereas the traditional scan-based technique can achieve only a speedup of about 2-3-which means that the proposed technique is about 500 times faster than the traditional scan-based technique. Such results are supported by theoretical performance analysis. This speed increase has been achieved without excessive increase in FPGA resource overhead, for exa

关键词： FIELD programmable gate arrays INTEGRATED circuits ROUNDING errors gate array circuits

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A Programmable Receiver for Communication Systems and Its Application to Impulse Radio

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JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING 2009年第unknown期2009卷 1-5页

作者： Merz, Roman Botteron, Cyril Chastellain, Frederic Farine, Pierre-Andre Univ Neuchatel CH-2000 Neuchatel Switzerland EPFL Elect & Signal Proc Lab CH-2000 Neuchatel Switzerland

The design of a programmable receiver for an ultra wideband (UWB) communication is presented. The receiver is using a fast analog to digital converter (ADC) and a field programmable gate array (FPGA) allowing a rapid performance evaluation for various system architectures and signal processing algorithms. To demonstrate the performance and the versatility of the receiver, a simple communication system and a localization system are implemented. The accuracy of the latter is presented for an indoor environment. Copyright (C) 2009 Roman Merz et al.

关键词： BROADBAND communication systems DIGITAL-to-analog converters FIELD programmable gate arrays PROGRAMMABLE logic devices gate array circuits SIGNAL processing -- Digital techniques DIGITAL communications LINE receivers (Integrated circuits) DIGITAL electric filters

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Quad-level bit-stream adders and multipliers with efficient FPGA implementation

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ELECTRONICS LETTERS 2008年第12期44卷 722-723页

作者： Ng, C. W. Wong, N. Ng, T. S. Univ Hong Kong Dept Elect & Elect Engn Hong Kong Hong Kong Peoples R China

Novel adder and multiplier circuits for bit-stream signal processing customised for quad-level sigma-delta modulated signals are proposed. Compared with existing sorter-based quad-level sigma-delta adders and multipliers, the proposed implementation is more resource-efficient (> 76% hardware savings) and faster (> 93% higher clock frequency) when realised on state-of-the-art FPGA architecture featuring six-input look-up tables.

关键词： Signal processing Information measurement Field programmable gate arrays gate array circuits Programmable logic devices Logic devices

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The promise of high-performance reconfigurable computing

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COMPUTER 2008年第2期41卷 69-+页

作者： El-Ghazawi, Tarek El-Araby, Esam Huang, Miaoqing Gaj, Kris Kindratenko, Volodymyr Buell, Duncan George Washington Univ Dept Comp & Elect Engn Washington DC 20052 USA George Washington Univ HPCL Washington DC 20052 USA Univ Illinois Natl Ctr Supercomp Applicat Innovat Syst Lab Urbana IL USA Univ S Carolina Dept Comp Sci & Engn Columbia SC 29208 USA

In the past few years, high-performance computing vendors introduced many systems containing both microprocessors and field-programmable gate arrays. In all these architectures, the main application executes on the microprocessors, while the FPGAs handle kernels with long execution times but that lend themselves to hardware implementations. The authors' research revealed that HPRCs can achieve up to four orders of magnitude improvement in performance, up to three orders of magnitude reduction in power consumption, and a two orders of magnitude savings. in cost and size requirements.

关键词： HIGH performance computing COMPUTER architecture gate array circuits MOLECULAR dynamics BIOINFORMATICS CRYPTOGRAPHY

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Influences of low temperature silicon nitride films on the electrical performances of hydrogenated amorphous silicon thin film transistors

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JOURNAL OF PHYSICS D-APPLIED PHYSICS 2008年第24期41卷 245502 (6p-245502 (6p页

作者： Huang, Jung-Jie Liu, Chan-Jui Lin, Hung-Chien Tsai, Cheng-Ju Chen, Yung-Pei Hu, Guo-Ren Lee, Cheng-Chung Ind Technol Res Inst Display Technol Ctr Dept Thin Film Transistor Technol Hsinchu 310 Taiwan

Influences of silicon nitride (SiNx) films on the electrical performances of hydrogenated amorphous silicon thin film transistors (a-Si : H TFTs) are studied. Relatively low temperature (200 degrees C) SiNx films are prepared by plasma enhanced chemical vapour deposition at different radio-frequency powers. Results indicate that the SiNx films at a radio-frequency power of 340 W (Power density = 1.96 x 10(-1) W cm(-2)) are near-stoichiometric and have better interface quality. Therefore, a-Si : H TFTs with this SiNx gate dielectric layer have a high field effect mobility and sustain the bias stress. The field effect mobility is 0.59 cm(2) V-1 s(-1) and the threshold voltage shift after a constant voltage stress (CVS) for 2.8 h is 3.18V. The electrical degradation mechanism of a-Si : H TFTs is studied from the capacitance-voltage measurement. The degradation of the a-Si : H TFT after CVS is due to the defect generation in the SiNx gate dielectric and a-Si : H active layers. However, when the surface roughness of the SiNx film is poor, the degradation from the a-Si : H/SiNx interface is predominated. Therefore, if the SiNx film is used as a gate dielectric layer to fabricate a-Si : H TFTs, the surface roughness and chemical composition of the SiNx film should be considered simultaneously.

关键词： SILICON nitride THIN film transistors LOW temperatures TEMPERATURE effect AMORPHOUS substances gate array circuits CHEMICAL vapor deposition RADIO frequency

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