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EE-EVALUATION ENGINEERING 2006年第4期45卷 18-+页

作者： Lecklider, T

The article focuses on the development of very large field programmable gate arrays (FPGA). The reason for the interest in FGPA is that they have passed the point where their cost was hard to justify. There are FPGA that can only be programmed once. These one-time-programmable devices have the advantage of working from the instant the power is turned on. FPGA based on SRAM program storage are also available. Advantages include zero programming time and zero stock of programmed parts. The third type of FPGA is based on flash memory cells. Flash has the advantage of working from power-on without loading a program each time.

关键词： FIELD programmable gate arrays RANDOM access memory FLASH memories (Computers) gate array circuits COMPUTER storage devices

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gate voltage and oxide thickness dependence of progressive wear-out of ultra-thin gate oxides

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MICROELECTRONICS RELIABILITY 2006年第9-11期46卷 1603-1607页

作者： Pompl, T. Kerber, A. Roehner, M. Kerber, M. Infineon Technol AG D-81739 Munich Germany

The progressive wear-out of a breakdown path in ultra-thin gate oxides depends on oxide thickness and follows the intrinsic voltage acceleration model of time to breakdown. The quantification of progressive wear-out i... 详细信息

关键词： OXIDES gate array circuits INTEGRATED circuits ELECTRIC potential

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Design and quantitative analysis of parametrisable eFPGA-architectures for arithmetic

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ADVANCES IN RADIO SCIENCE 2006年 4卷 251-257页

作者： Neumann, B. von Sydow, T. Blume, H. Noll, T. G. Rhein Westfal TH Aachen Chair Elect Engn & Comp Syst D-52062 Aachen Germany

Future SoCs will feature embedded FPGAs (eFPGAs) to enable flexible and efficient implementations of high-throughput digital signal processing applications. Current research projects on and emerging products containing FPGAs are mainly based on "standard FPGA"-architectures that are optimised for a very wide range of applications. The implementation costs of these FPGAs are dominated by a very complex interconnect network. This paper presents a method to improve the efficiency of eFPGAs by tailoring them for a certain application domain using a parametrisable architecture template derived from the results of a systematic evaluation of the requirements of the application domain Two different architectures are discussed, a reference architecture to illustrate the methodology and possible optimisation measures as well as a specialised arithmetic-oriented eFPGA for applications like correlators, decoders, and filters. For the arithmetic-oriented architecture, a novel logic element (LE) and a special interconnect architecture that was designed with respect to the connectivity characteristics of regular datapaths, are presented. For both architecture templates, physically optimised implementations based on an automatic design approach have been created. As a first cost comparison of these implementations with standard FPGAs, the LE-density (number of logic elements per mm2) is evaluated. For the arithmetic-oriented architecture, the LE-density could be increased by an order of magnitude compared to standard architectures.

关键词： FIELD programmable gate arrays SIGNAL processing -- Digital techniques gate array circuits LOGIC devices DIGITAL communications COMPUTER architecture

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FPGA-based real-time image segmentation for medical systems and data processing

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2006年第4期53卷 2097-2101页

作者： Dillinger, P. Vogelbruch, J. F. Leinen, J. Suslov, S. Patzak, R. Winkler, H. Schwan, K. Res Ctr Julich Cent Res Inst Elect D-52425 Julich Germany Array Elect GmbH D-85658 Egmating Germany

Three-dimensional (3-D) image segmentation is one of the most demanding tasks in image processing. The applications comprise industrial and scientific tasks. Due to the high data volume, advanced algorithms cannot be processed on standard hardware in real time. We propose the perfectly parallelizable 3-D Gray-Value Structure Code (3-D-GSC) for image segmentation on a new FPGA custom machine. This 128-Bit FPGA coprocessing board features an up-to-date Virtex-II Pro architecture, two large independent DDR-SDRAM channels, two fast independent ZBT-SRAM channels, and PCI-X bus and CameraLink interfaces. The hardware speeds up the segmentation algorithm and allows processing of a 5123 image (16 bpv) in about 2 s.

关键词： FIELD programmable gate arrays gate array circuits INTEGRATED circuits ELECTRONIC data processing INFORMATION storage & retrieval systems COMPUTER input-output equipment COMPUTERS COMPUTER systems THREE-dimensional imaging IMAGING systems

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Majority logic gate for magnetic quantum-dot cellular automata

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SCIENCE 2006年第5758期311卷 205-208页

作者： Imre, A Csaba, G Ji, L Orlov, A Bernstein, GH Porod, W Univ Notre Dame Dept Elect Engn Ctr Nano Sci & Technol Notre Dame IN 46556 USA Tech Univ Munich Inst Nanoelect D-80333 Munich Germany

We describe the operation of, and demonstrate logic functionality in, networks of physically coupled, nanometer-scale magnets designed for digital computation in magnetic quantum-dot cellular automata (MQCA) systems. MQCA offer low power dissipation and high integration density of functional elements and operate at room temperature. The basic MQCA logic gate, that is, the three-input majority logic gate, is demonstrated.

关键词： gate array circuits CELLULAR automata MAGNETISM QUANTUM theory NANOSTRUCTURED materials MAGNETS MAGNETIC materials INTEGRATED circuits SEQUENTIAL machine theory

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Pulling strings

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SCIENCE 2006年第5805期314卷 1552-1553页

作者： Fontana, Walter Harvard Univ Dept Syst Biol Boston MA 02115 USA

In the past decade, DNA or RNA sequences have been used to find solutions in combinatorial problems by self-assembly to encode complete decision trees for simple games like tic-tac-toe and to build programmable sensors of cellular states. Fontana discusses a toolkit of DNA-based devices which can be used for computational circuits.

关键词： DNA gate array circuits NUCLEOTIDE sequence SUBSTITUTION reactions NUCLEIC acid analysis INTEGRATED circuits GENES CHEMICAL reactions NUCLEOTIDE analysis

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Where have all the transistors gone?

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SCIENCE 2006年第5758期311卷 183-184页

作者： Cowburn, RP Univ London Imperial Coll Sci Technol & Med Blackett Phys Lab London SW7 2BW England

A universal logic gate has been constructed with magnetic nanostructures. Such devices could lead to a new generation of microelectronics.

关键词： gate array circuits MICROELECTRONICS DIGITAL electronics NANOSTRUCTURES TRANSISTORS ELECTRONS INTEGRATED circuits SPINTRONICS CELLULAR automata

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Extendable and dynamically reconfigurable multi-protocol firewall

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INTERNATIONAL JOURNAL OF SOFTWARE ENGINEERING AND KNOWLEDGE ENGINEERING 2005年第2期15卷 363-371页

作者： Ly, S Bigdeli, A Univ Auckland Dept Elect & Comp Engn Embedded Syst Res Grp Auckland 1 New Zealand

Security issues within a networking environment are critical, as attacks or intrusions can come from many different sources. Firewalls are an effective tool used for intrusion detection and provide protection against attacks on a system or network. In the past, protection barriers for a local network have been provided using software solutions. Emerging multi-gigabit networking technology and the high uptake of gigabit Ethernet has rendered these solutions inefficient as it cannot cope with the high data rate. In this paper, a new approach using reconfigurable hardware such as Field Programmable gate arrays is proposed to provide the flexibility and performance required for a gigabit firewall. The solution is extendable, has low cost and is capable of scanning multiple protocols. The design approach will allow it to be easily ported over to another family of chips with no or minor modification.

关键词： FIREWALLS (Computer security) COMPUTER network security COMPUTER security ETHERNET (Local area network system) FIELD programmable gate arrays gate array circuits PROGRAMMABLE logic devices

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Digital field programmable gate array-based lock-in amplifier for high-performance photon counting applications

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REVIEW OF SCIENTIFIC INSTRUMENTS 2005年第9期76卷 3112-1-3112-8页

作者： Restelli, A Abbiati, R Geraci, A Politecn Milan Dept Elect & Informat Technol I-20133 Milan Italy

In the past few years the availability of low-cost, high-performance digital configurable devices [digital signal processors (DSP) and field programmable gate arrays (FPGAs) above all] has extended the application of digital signal processing to a larger field of instrumentation. In particular, the phase-sensitive detection (PSD) technique, which is at the heart of lock-in amplifiers, substantially benefits from digital implementation, especially by the use of configurable devices, both in terms of architectural efficiency and achievable performance. In this paper we describe the design and realization of a digital lock-in amplifier devoted to high-performance photon counting applications based on a PSD section implemented in a FPGA device. Among the main features of the proposed digital instrument are reconfigurability, a wide range of operative parameters, very large functional performances, and extremely low cost. The prototype has been experimentally tested and the results fully comply with the goal design specifications. (c) 2005 American Institute of Physics.

关键词： FIELD programmable gate arrays PHOTON detectors PHOTONS gate array circuits SCIENTIFIC apparatus & instruments

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A high-speed optical mark reader hardware implementation at low cost using programmable logic

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REAL-TIME IMAGING 2005年第1期11卷 19-30页

作者： Hussmann, S Deng, PWP Univ Appl Sci Westkuste Dept Elect Engn & Informat Technol D-25746 Heide Germany Univ Auckland Sch Engn Dept Elect & Comp Engn Auckland 1 New Zealand

In today's fast-paced information-driven society, the need for accurate, timely, and cost-effective data collection is very critical. Optical mark reader (OMR) systems can be used to achieve these aspects. This paper describes the development of a low-cost and high-speed OMR system prototype for marking multiple-choice questions. The novelty of this approach is the implementation of the complete system into a single low-cost Field Programmable gate array (FPGA) to achieve the high processing speed. Effective mark detection and verification algorithms have been developed and implemented to achieve real-time performance at low computational cost. The OM R is capable of processing a high-resolution CCD linear sensor with 3456 pixels at 5000 frame/s at the effective maximum clock rate of the sensor of 20 MHz (4 x 5 MHz). The performance of the prototype system is tested for different marker colours and marking methods. At the end of the paper the proposed OMR system is compared with commercially available systems and the pro and cons are discussed. (c) 2005 Elsevier Ltd. All rights reserved.

关键词： FIELD programmable gate arrays COST effectiveness gate array circuits DIGITAL cameras

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