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DC pulse hot-carrier-stress effects on gate-induced drain leakage current in n-channel MOSFETs

IEEE TRANSACTIONS ON ELECTRON DEVICES 2001年第12期48卷 2746-2753页

作者： Chen, JH Wong, SC Wang, YH Natl Cheng Kung Univ Dept Elect Engn Tainan 70101 Taiwan Taiwan Semicond Mfg Co Hsinchu 300 Taiwan

The dc pulse hot-carrier-stress effects on the degradation in gate-induced drain leakage (GIDL) current in a high field regime and the mechanisms of stress-induced degradation are studied. In this paper, we investigate de pulse stress parameters in GIDL which include frequency, rise/fall time, and amplitude of stressing pulse. The contribution of hot-hole injection, interface state generation, and hot-electron injection in a period of transient stress are identified. It is found that the device degradation increases with increased pulse frequency under maximum gate current stress, while it decreases with reduced pulse frequency under maximum substrate current stress. This work is useful for de pulse hot-carrier-stress reliability analysis under circuit operation.

关键词： HOT carriers gate array circuits SCIENTIFIC experimentation

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Accelerating molecular dynamics simulations with configurable circuits

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 2006年第3期153卷 189-195页

作者： Gu, Y. VanCourt, T. Herbordt, M. C. Boston Univ Dept Elect & Comp Engn Boston MA 02215 USA

Molecular dynamics (MD) is of central importance to computational chemistry. Here the authors show that MD can be implemented efficiently on a commercial off-the-shelf (COTS) field programmable gate array (FPGA) board, and that speed-ups from 31 x to 88 x over a PC implementation can be obtained. Although the extent of speed-up depends on the stability required, 46x can be obtained with virtually no detriment, and the upper end of the range is apparently viable in many cases. The authors sketch the FPGA implementations and describe the effects of precision on the trade-off between the performance and quality of the MD simulation.

关键词： MOLECULAR dynamics FIELD programmable gate arrays CHEMISTRY COMPUTER simulation DYNAMICS PROGRAMMABLE logic devices gate array circuits ANALYTICAL mechanics PHYSICAL sciences ENGINEERING

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Real-Time Differential Signal Phase Estimation for Space-Based Systems using FPGAs

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IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS 2013年第2期49卷 1192-1209页

作者： Lu, Shiting (Justin) Siqueira, Paul Vijayendra, Vishwas Chandrikakutty, Harikrishnan Tessier, Russell Univ Massachusetts Dept Elect Engn Amherst MA 01003 USA Altera Corp High Speed Serial Protocol IPs San Jose CA USA

High performance and reliability are important aspects of space-based systems. In many cases correct system functionality must be continuously monitored to ensure the validity of collected data. In this research we develop a new digital circuit which can detect minute phase differences in time-varying analog signals. These phase shifts can be determined for both a single channel input versus a known model of the signal and across two channels with simultaneously-sampled data. Phase shift data can be used in spaceborne systems to either confirm correct system operation or identify potential problems. Current systems primarily transfer data to the Earth for error checking rather than performing error analysis in real-time. The benefits of our field-programmable gate array (FPGA)-based approach are evaluated using a 3 gigasamples per second (GSamp/s) data acquisition system developed as part of the NASA Surface Water Ocean Topography (SWOT) initiative. Phase calculations with an error of less than 0.021 deg (0.006% of 360 deg) are determined using our adaptive approach. The high accuracy of differential phase detection allows for the real-time monitoring of environmental metrics, such as temperature fluctuations, which affect signal phase.

关键词： REAL-time control SPACE-based radar gate array circuits NUMERICAL analysis MATHEMATICAL statistics

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Running an FPGA at ASIC speed

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EDN 2007年第14期52卷 53-+页

作者： Park, Edwin C. Won, Martin S. Rice Univ Houston TX 77251 USA Univ Calif Santa Barbara Santa Barbara CA 93106 USA

The hardware-emulation team at Texas Instruments (***) is getting wordabout its next project: developing a prototype of the modem of a baseband-processor ASIC fornext-generation wireless handsets. The prototype is necessary to help the software team test itscode using real hardware as soon as possible, because the processor itself won't be ready foranother 12 to 14 months. Getting this head start on software development is key to the productschedule, because the software effort represents most of the overall engineering effort.

关键词： Modems Cell phones Field programmable gate arrays Memory maps (Computer science) gate array circuits

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A NOR-AND quantum running gate molecule

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CHEMICAL PHYSICS LETTERS 2009年第1-3期472卷 74-79页

作者： Renaud, N. Ito, M. Shangguan, W. Saeys, M. Hliwa, M. Joachim, C. Ctr Elaborat Mat & Etud Struct CNRS Nanosci Grp F-31055 Toulouse France Fujitsu Labs Ltd Nanotechnol Res Ctr Atsugi Kanagawa 2430197 Japan Natl Univ Singapore Dept Chem & Biomol Engn Singapore 117576 Singapore Univ Hassan II Mohammedia Fac Sci Ben Msik Casablanca Morocco Inst Mat Res & Engn Singapore 117602 Singapore

A [1,5]-dinitro-anthracene molecule performs a NOR or AND digital logic function depending of the polarity of the bias voltage applied to the molecule. Its design is based on the fact that a quantum system can demonstrate a Boolean like dependent Rabi oscillation frequency while this frequency is controlled by well unidentified parameters of its Hamiltonian therefore used as logic inputs for the logic gate. This quantum Hamiltonian computing (QHC) approach permits a systematic design of quantum driven classical logic gates whose quantum structure can be mapped on the electron pi system of a polyaromatic molecule. The output of such molecule logic gate is encoded in the tunnelling current I passing through the board of the molecule. Supposed to be interconnected to two semi-infinite metallic atomic wires, our NOR (AND) dinitro-anthracene molecule presents a two orders of magnitude difference between its logic levels '1' and '0' as demonstrated by calculating its full low current I(theta(1), theta(2)) logic surface where theta(1) and theta(2) are the NO2 conformation angles encoding for a classical '0' or '1' logic input on the molecule. (C) 2009 Elsevier B. V. All rights reserved.

关键词： gate array circuits MOLECULES ANTHRACENE QUANTUM theory HAMILTONIAN systems CONFORMATIONAL analysis NANOWIRES AROMATIC compounds

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Temperature dependent drain current model for gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for wide operating temperature range

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MICROELECTRONICS RELIABILITY 2012年第6期52卷 974-983页

作者： Kumari, Vandana Saxena, Manoj Gupta, R. S. Gupta, Mridula Univ Delhi Dept Elect Sci Semicond Device Res Lab New Delhi 110021 India Univ Delhi Deen Dayal Upadhyaya Coll Dept Elect New Delhi 110015 India Maharaja Agrasen Inst Technol Dept Elect & Commun Engn Delhi 110086 India

This paper presents two dimensional temperature dependent analytical model of gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET and compares it with the simulated data using ATLAS 3D device simulator for wide operating temperature i.e. 300-500 K for channel length down to 32 nm technology node. In this work, a temperature dependent analytical expression of drain current for sub-threshold region to saturation region has been developed. Lower sub-threshold slope and reduced leakage current in case of ISESON MOSFET (as compared to ISE and SON) results in better NMOS inverter performance and hence ISESON can be widely used in CCD camera as well as for fast switching applications. Further, we have also investigated the impact of temperature on electrical characteristics of ISESON MOSFET which are important for analog applications. (C) 2011 Elsevier Ltd. All rights reserved.

关键词： gate array circuits TEMPERATURE effect ELECTRIC currents ELECTRIC insulators & insulation METAL oxide semiconductor field-effect transistors SIMULATION methods & models CCD cameras

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A comparison of advanced transport models for the computation of the drain current in nanoscale nMOSFETs

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SOLID-STATE ELECTRONICS 2009年第12期53卷 1293-1302页

作者： Palestri, P. Alexander, C. Asenov, A. Aubry-Fortuna, V. Baccarani, G. Bournel, A. Braccioli, M. Cheng, B. Dollfus, P. Esposito, A. Esseni, D. Fenouillet-Beranger, C. Fiegna, C. Fiori, G. Ghetti, A. Iannaccone, G. Martinez, A. Majkusiak, B. Monfray, S. Peikert, V. Reggiani, S. Riddet, C. Saint-Martin, J. Sangiorgi, E. Schenk, A. Selmi, L. Silvestri, L. Toniutti, P. Walczak, J. Univ Udine DIEGM IU NET I-33100 Udine Italy Univ Glasgow Glasgow Lanark Scotland Univ Bologna IU NET ARCES Bologna Italy Univ Paris Sud CNRS IEF Orsay France Univ Bologna ARCES Cesena Italy ETH CH-8092 Zurich Switzerland Numonyx R&D Technol Dev I-20041 Agrate Brianza Italy Univ Pisa IU NET Pisa Italy Warsaw Univ Technol Warsaw Poland ST Microelect Crolles France CEA MINATEC LETI F-38054 Grenoble France

In this paper we compare advanced modeling approaches for the determination of the drain current in nanoscale MOSFETs. Transport models range from drift-diffusion to direct solutions of the Boltzmann-Transport-Equation with the Monte-Carlo method. Template devices representative of 22 nm Double-gate and 32 nm Single-gate Fully-Depleted Silicon-On-Insulator transistors were used as a common benchmark to highlight the differences between the quantitative predictions of different approaches. Using the standard scattering and mobility models for unstrained silicon channels and pure SiO2 dielectrics, the predictions of the different approaches for the 32 nm template are quite similar. Simulations of the 22 nm device instead, are much less consistent, particularly those achieved with MC simulators. Comparison with experimental data for a 32 nm device shows that the modeling approach used to explain the mobility reduction induced by the high-kappa dielectric is critical. In the absence of a clear understanding of the impact of high-kappa stack on transport, different models, all providing agreement with the experimental low-field mobility, predict quite different drain currents in saturation and in the sub-threshold region. (C) 2009 Elsevier Ltd. All rights reserved.

关键词： COMPARATIVE studies TRANSPORT theory (Mathematics) NANOELECTRONICS METAL oxide semiconductor field-effect transistors MONTE Carlo method gate array circuits SILICON-on-insulator technology ELECTRON scattering ELECTRON mobility

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DESIGNING AN ACCESSIBLE BOARD

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EDN 2009年第19期54卷 24-29页

作者： Wilson, Ron

The article discusses the board design that is accessible for debugging and verification during the development of the product. Particular focus is given to a systematic approach for attaining this goal, which involves understanding the functions of the board and preparing measures to verify the proper state of these functions. Also discussed is the advantage of field-programmable gate arrays (FPGAs) over central processing units (CPUs).

关键词： Integrated circuits Field programmable gate arrays Centralized processing (Libraries) gate array circuits Programmable logic devices

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Remote carrier trapping in FinFETs with ONO buried layer: Temperature effects

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MICROELECTRONICS RELIABILITY 2013年第3期53卷 386-393页

作者： Chang, Sung-Jae Bawedin, Maryline Xiong, Wade Lee, Jong-Hyun Lee, Jung-Hee Cristoloveanu, Sotin Grenoble INP Minatec IMEP LAHC F-38016 Grenoble France Univ Montpellier 2 IES Montpellier France AMD D-01109 Dresden Germany Kyungpook Natl Univ Taegu South Korea

The charge trapping mechanisms are studied at room and high temperature in advanced SOI FinFETs fabricated on SiO2-Si3N4-SiO2 (ONO) multi-layer buried insulator (BOX). By applying appropriate back-gate and/or drain bias, the buried nitride layer can trap charges. The coupling mechanism between front and back interfaces enables the front-channel drain current to reflect the presence or absence of trapped/injected charges in the BOX. In this work, the charge trapping/detrapping is induced by a constant drain or back-gate bias or during the scanning of the back-gate voltage. According to the polarity of the trapped charges and their location along the channel, various current levels are observed leading to a memory effect. In order to clarify the charge trapping and coupling mechanisms, the temperature of operation was used as additional experimental parameter. The amount of trapped charges depends not only on the bias conditions but also on temperature and fin geometry. We discuss the 3D coupling effects between the channel and the remote trapped charges. (C) 2012 Elsevier Ltd. All rights reserved.

关键词： ION traps HIGH temperatures POWER transistors gate array circuits SILICON oxide NITRIDES MAGNETIC couplings

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DESIGN AND SIMULATION OF A HIGH-RELIABILITY NONVOLATILE CMOS EEPROM MEMORY CELL COMPATIBLE WITH SCALING-DOWN TRENDS

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INTERNATIONAL JOURNAL OF ELECTRONICS 1992年第1期72卷 73-87页

作者： ELHENNAWY, A King Abdul-Aziz University Jeddah P.O. Box 9028 Saudi Arabia

A simple but high-reliability non-volatile electrically-programmable and erasable memory cell (EEPROM) based on a non-avalanche injection mechanism is presented. This memory cell is composed of a double gate CMOS inverter. Circuit design allows fast programming and erasing (t(p) < 20 ms) with a single supply voltage of 5 V (at MOSFET channel length L = 2-mu-m and width = 20-mu-m). It employs a non-avalanche injection mechanism which guarantees a minimized oxide and interface degradation which leads to higher reliability and better operation stability. The EEPROM circuit latches the input data owing to the bidirectional hot carrier gate current. In this EEPROM, the majority of drawbacks of recent memories such as poor stability, long programming time, low reliability and the necessity of using two power supplies are removed. We then introduce a powerful simulation technique to compute V0(t), the output voltage, during programming and erasing cycles and also the programming time t(p). Computations have indicated good compatibility of the present EEPROM with the recent scaling-down trends in VLSI technology.

关键词： COMPUTER storage devices COMPUTER programming COMPLEMENTARY metal oxide semiconductors gate array circuits INTERFACE circuits

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