The authors demonstrate the fabrication of solid state and vacuum electronic devices using carbon nanotubes as the active channel and emitters. Single wall and multiwall carbon nanotubes (CNT) are deposited directly o...
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The authors demonstrate the fabrication of solid state and vacuum electronic devices using carbon nanotubes as the active channel and emitters. Single wall and multiwall carbon nanotubes (CNT) are deposited directly on substrates using chemical vapour deposition (CVD) and plasma enhanced chemical vapour deposition (PECVD), respectively. The fabrication of top gate and side gate field effect transistors is demonstrated using single wall CNTs. Vertically aligned multiwall CNTs are used to fabricate field emitter arrays or micro-gated field emitters, which have potential application in field emission displays, microwave amplifiers or electron guns.
A digital to analogue converter (DAC) based on a single-electron tunnelling transistor (SETT) is proposed. The proposed scheme fully utilises the Coulomb blockade effect and only a SETT and n + 1 capacitors are necess...
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A digital to analogue converter (DAC) based on a single-electron tunnelling transistor (SETT) is proposed. The proposed scheme fully utilises the Coulomb blockade effect and only a SETT and n + 1 capacitors are necessary for an n-bit DAC implementation. Using this scheme, a 4-bit DAC is demonstrated by means of simulation.
Linear Decision Diagrams (LDDs) are used in the paper as an intermediate format that allows us to quickly generate the circuit netlist from HDL (hardware description language), such as Verilog, or transform it to HDL ...
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Linear Decision Diagrams (LDDs) are used in the paper as an intermediate format that allows us to quickly generate the circuit netlist from HDL (hardware description language), such as Verilog, or transform it to HDL description for further ASIC or FPGA synthesis and verification. The results of an extensive experimental study (on memory requirements, run time to convert LDD intermediate format to/from HDL, and verification via simulation) are reported here.
The influence of 8 MeV electrons on the threshold voltage (V-TH), transconductance (g(m)) and mobility (mu) of n-channel depletion metal-oxide semiconductor field-effect transistors (MOSFETs) irradiated at gate bias, ...
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The influence of 8 MeV electrons on the threshold voltage (V-TH), transconductance (g(m)) and mobility (mu) of n-channel depletion metal-oxide semiconductor field-effect transistors (MOSFETs) irradiated at gate bias, V-GS = +2, 0 and -2 V, has been studied in the dose range of 0.5-31 kGy. The measurements performed after irradiation showed considerable decrease in V-TH, g(m) and mu. The densities of interface trapped charge (DeltaN(it)) and oxide trapped charge (DeltaN(ot)) for irradiated devices have been estimated from the subthreshold measurements. It has been found that DeltaN(ot) is higher than DeltaN(it). The mobility of carriers (mu) in the n-channel was estimated from the peak transconductance (g(mPeak)) and it was found that mu decreased by around 68.5-73.5% after exposure to the total dose of 31 kGy. Mobility degradation coefficients due to interface traps (alpha(it)) and oxide trapped charge (alpha(ot)) were estimated and it was found that the mobility degradation was mainly due to DeltaN(it) and the effect of DeltaN(ot) was negligible.
A reconfigurable multiplier design for low-power field programmable gatearrays (FPGAs) is presented. Power consumption reduction is achieved through varying the depth of pipeline of the multiplier. The multiplier inc...
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A reconfigurable multiplier design for low-power field programmable gatearrays (FPGAs) is presented. Power consumption reduction is achieved through varying the depth of pipeline of the multiplier. The multiplier incorporates a capability of configuring itself dynamically, thus, is suitable for FPGA type of design.
A simple and reliable method to determine a MOSFET's gate resistance (R-in) directly from S-parameter measurements is presented. The extracted data agree well with the data predicted by transmission line theory an...
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A simple and reliable method to determine a MOSFET's gate resistance (R-in) directly from S-parameter measurements is presented. The extracted data agree well with the data predicted by transmission line theory and show that the main contribution of the transistor's input resistance (R-in) comes from the gate electrode resistance for devices with channel length below 0.2 mum.
Post-layout automatic analysis of Flux-1 microprocessor, a representative random logic RSFQ chip of more than 5000 gate complexity, allowed us to extract important layout parameters such as gate density, Josephson jun...
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Post-layout automatic analysis of Flux-1 microprocessor, a representative random logic RSFQ chip of more than 5000 gate complexity, allowed us to extract important layout parameters such as gate density, Josephson junction density and gate/wiring/unused area ratios. A scaling model is presented to predict the area required to layout a given number of random logic gates. When applied to Flux-1 chip itself, which occupies 88.6 mm(2) in the current TRW's 4 kA/cm(2) J110D technology, this model predicts that it can be shrunk by almost a factor of two in area to 49 mm(2) if moved to a next-generation J110E technology with 8 kA/cm(2) junctions. This information enables us to confidently floorplan random logic chips to be implemented in future advanced JJ technologies. It can also provide directions for JJ technology improvements leading to the maximum positive impact on RSFQ chip density.
We propose an experimental method of determining the equivalent oxide thickness (EOT) of gate insulators based on the principle that the capacitance associated with the bandbendings in the Si substrate and the gate (S...
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We propose an experimental method of determining the equivalent oxide thickness (EOT) of gate insulators based on the principle that the capacitance associated with the bandbendings in the Si substrate and the gate (Si capacitance) depends only on the Si surface field. To do this we experimentally obtained the Si surface field by using the capacitance-voltage (CV) integration method, and we used x-ray reflectometry to measure the physical thickness of thermal oxides. We then determined the relationship between the Si capacitance and the Si surface field. The relationship among the Si capacitance, the Si surface field, the EOT, and gate voltage minus the flatband voltage was also experimentally obtained. From these two relationships, we produce ideal CV curves for any given EOT and determined EOTs in such a way that the ideal CV curves fit best with the experimental results. Accordingly, our method is free of errors that accompany modeling the quantum mechanics of the gate electrode and Si substrate, and any errors that it does contain are independent of the film thickness. We further simplified the method for practical application by approximating the above relationships using rational polynomials. The results obtained by this simplified method were in good agreement with the experiments for the whole range of thicknesses. In contrast, the conventional quantum mechanical simulators produced CV curves that showed no small difference from the measured ones in the case of thin oxides in the 1-nm-thick range, and led to an overestimate of the EOT. Our method of EOT derivation provides an important basis for developing high-performance metal-oxide-semiconductor transistors. (C) 2002 American Institute of Physics.
'Tapered gate' is a device sizing methodology to improve the performance of critical paths in stacked circuit configurations. This paper presents a detailed study of the performance leverage of tapered gate in...
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'Tapered gate' is a device sizing methodology to improve the performance of critical paths in stacked circuit configurations. This paper presents a detailed study of the performance leverage of tapered gate in a partially depleted silicon-on-insulator (PD/SOI) technology. It is shown that the reduced junction capacitance in a PD/SOI device renders the series resistance reduction of the lower transistors in the stack more effective. The effects are also shown to be more pronounced for low-V-T cases. The study demonstrates that tapered gate remains a viable device sizing technique/methodology for improving performance in a PD/SOI technology.
We study the performance of a lateral p-n junction quantum-well edge-emitting laser-transistor with an extra gate contact. The incorporation of the gate contact provides an opportunity to control the threshold current...
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We study the performance of a lateral p-n junction quantum-well edge-emitting laser-transistor with an extra gate contact. The incorporation of the gate contact provides an opportunity to control the threshold current and output optical power by the gate voltage. The application of negative gate voltages can lead to a substantial decrease in the threshold current. This is due to the confinement of the electrons injected into the p-type portion of the quantum well serving as the active region. Using the developed device model, we calculate the laser-transistor threshold and output characteristics. We also estimate the device cutoff modulation frequency associated with the gate recharging. (C) 2002 American Institute of Physics.
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