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Threshold voltage shift prediction for gate bias stress on amorphous InGaZnO thin film transistors

MICROELECTRONICS RELIABILITY 2012年第9-10期52卷 2215-2219页

作者： Park, Suehye Cho, Edward Namkyu Yun, Ilgu Yonsei Univ Dept Elect & Elect Engn Seoul 120749 South Korea

The demand for amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) has increased due to the high mobility and suitability for low temperature fabrication. A prediction of the threshold voltage shift (Delta V-th) under bias stress is required for the commercial use of a-IGZO TFTs. We have investigated effects of the channel length and alternating pulse bias (positive and negative gate bias stress in sequence) with different positive gate bias values (V-GS <-) on Delta V-th. We found that Delta V-th increases as the channel length decreases or VGS+ increases, due to the increase in the charge trapping rate. Finally, the degradation behaviors of a-IGZO TFTs are predicted. (C) 2012 Elsevier Ltd. All rights reserved.

关键词： gate array circuits ELECTRIC potential STRAINS & stresses (Mechanics) AMORPHOUS substances ZINC oxide THIN film transistors LOW temperatures MICROFABRICATION

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Computational Lateral Flow Biosensor for Proteins and Small Molecules: A New Class of Strip Logic gates

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ANALYTICAL CHEMISTRY 2012年第15期84卷 6321-6325页

作者： Chen, Junhua Fang, Zhiyuan Lie, Puchang Zeng, Lingwen Chinese Acad Sci Key Lab Regenerat Biol S China Inst Stem Cell Biol & Regenerat Med Guangzhou Inst Biomed & Hlth Guangzhou 510530 Guangdong Peoples R China

The first example of strip logic gates ("OR" and "AND" functions) for proteins and small molecules has been constructed on the basis of target-induced self-assembly of split aptamer fragments. Using thrombin and ATP as inputs, the corresponding split/integrated aptamers as molecular recognition elements, and gold nanoparticles as a tracer, the output signals can be directly visualized by observing the red bands on the test zones of the strips. The assay is simple, easy to perform, and cost-effective, allowing portable analysis at ambient temperature. The strip logic system is resistant to nonspecific interfering agents and can operate effectively even in human serum samples. Such logic strips hold great promise for application in intelligent point-of-care and in-field diagnostics.

关键词： BIOSENSORS PROTEINS gate array circuits MOLECULAR self-assembly APTAMERS THROMBIN ADENOSINE triphosphate GOLD nanoparticles

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A fast, direct x-ray detection charge-coupled device

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REVIEW OF SCIENTIFIC INSTRUMENTS 2009年第8期80卷 083302-083302-5页

作者： Denes, P. Doering, D. Padmore, H. A. Walder, J. -P. Weizeorick, J. Univ Calif Berkeley Lawrence Berkeley Lab Div Engn Berkeley CA 94720 USA Univ Calif Berkeley Lawrence Berkeley Lab Adv Light Source Div Berkeley CA 94720 USA Argonne Natl Lab Adv Photon Source Xray Sci Div Argonne IL 60439 USA

A charge-coupled device (CCD) capable of 200 Mpixels/s readout has been designed and fabricated on thick, high-resistivity silicon. The CCDs, up to 600 mu m thick, are fully depleted, ensuring good infrared to x-ray detection efficiency, together with a small point spread function. High readout speed, with good analog performance, is obtained by the use of a large number of parallel output ports. A set of companion 16-channel custom readout integrated circuits, capable of 15 bits of dynamic range, is used to read out the CCD. A gate array-controlled back end data acquisition system frames and transfers images, as well as provides the CCD clocks. (C) 2009 American Institute of Physics. [DOI: 10.1063/1.3187222]

关键词： CHARGE coupled devices DETECTORS IMAGE converters X-ray equipment gate array circuits INTEGRATED circuits

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Device and circuit level suppression techniques for random-dopant-induced static noise margin fluctuation in 16-nm-gate SRAM cell

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MICROELECTRONICS RELIABILITY 2010年第5期50卷 647-651页

作者： Lee, Kuo-Fu Li, Yiming Li, Tien-Yen Su, Zhong-Cheng Hwang, Chin-Hong Natl Chiao Tung Univ Dept Elect Engn Hsinchu 300 Taiwan Natl Chiao Tung Univ Inst Commun Engn Hsinchu 300 Taiwan Natl Nano Device Labs Hsinchu 300 Taiwan

In this study, a three-dimensional "atomistic" coupled device-circuit simulation is performed to explore the impact of process-variation-effect (PVE) and random-dopant-fluctuation (RDF) on static noise margin (SNM) of 16-nm complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) cells. Fluctuation suppression approaches, based on circuit and device viewpoints, are further implemented to examine the associated characteristics in 16-nm-gate SRAM cells. From the circuit viewpoint, the SNM of 8T planar SRAM is enlarged to 230 mV and the variation of SNM (sigma(SNM)) is reduced to 22 mV at a cost of 30% extra chip area. As for device level improvement, silicon-on-insulator (SOI) FinFETs replaced the planar MOSFETs in 6T SRAM is further examined. The SNM of 6T SOI FinFETs SRAM is 125 mV and the sigma(SNM) is suppressed significantly to 5.4 mV. However, development of fabrication process for SOI FinFET SRAM is crucial for sub-22 nm technology era. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： ELECTRIC circuits ELECTRONIC noise FLUCTUATIONS (Physics) RANDOM access memory gate array circuits CHARGE coupled devices SIMULATION methods & models COMPLEMENTARY metal oxide semiconductors METAL oxide semiconductor field-effect transistors

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Investigation on the thermal behavior of 0.15 μm gate-length In_0.4Al_0.6As/In_0.4Ga_0.6As MHEMT

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MICROELECTRONICS RELIABILITY 2012年第6期52卷 969-973页

作者： Lin, Che-Kai Chiu, Hsien-Chin Lin, Chao-Wei Kao, Hsuan-ling Chien, Feng-Tso Chang Gung Univ Dept Elect Engn Tao Yuan Taiwan Feng Chia Univ Dept Elect Engn Taichung 40724 Taiwan

In this study, we have successfully investigated the electrical performances of In0.4Al0.6As/In0.4Ga0.6As metamorphic high-electron-mobility transistor (MHEMT) at temperatures range from 275 K to 500 K comprehensively. By extracting the device S-parameters, the temperature dependent small signal model has been established. At room temperature, 0.15 mu m T-gate device with double delta-doping design exhibits f(T) and f(MAX) values of 103 GHz and 204 GHz at V-ds = 1 V, an extrinsic transconductance of 678 mS/mm, and a current density of 578 mA/mm associated with a high breakdown voltage of -13 V. Power measurements were evaluated at 40 GHz and the measured output power, linear power gain, and maximum power-added efficiency, were 7.12 dBm, 10.15 dB, and 23.1%, respectively. The activation energy (E-a) extracted from Arrhenius plots is = 0.34 eV at 150 <= T <= 350 K. The proposed device is promisingly suitable for millimeter-wave power application. (C) 2012 Elsevier Ltd. All rights reserved.

关键词： THERMAL analysis gate array circuits GALLIUM arsenide MODULATION-doped field-effect transistors TEMPERATURE effect ACTIVATION energy ARRHENIUS equation

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Temperature-dependent reverse-bias stress of normally-off GaN power FETs

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MICROELECTRONICS RELIABILITY 2013年第9-11期53卷 1486-1490页

作者： Giuliani, F. Delmonte, N. Cova, P. Menozzi, R. Univ Parma Dept Informat Engn I-43124 Parma Italy INFN Pavia I-27100 Pavia Italy

We show results of temperature-dependent reverse-bias step-stressing of normally-off high-power GaN FETs. In the range 250-350 K, the stress voltage at which the FETs fail catastrophically does not show a clear temperature dependence, while some correlation is observed with the initial leakage current value. Our results, consistent with other published reports, point to the activation of a deep gate-to-drain leakage path as the responsible for fatal device degradation at large values of the drain-gate reverse bias. (C) 2013 Elsevier Ltd. All rights reserved.

关键词： FIELD-effect transistors TEMPERATURE effect STRAINS & stresses (Mechanics) GALLIUM nitride STRAY currents FAILURE analysis (Engineering) gate array circuits

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RC hardened FPGA configuration SRAM cell design

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ELECTRONICS LETTERS 2004年第9期40卷 525-526页

作者： Wang, W Univ Wisconsin Dept Elect Engn & Comp Sci Milwaukee WI 53201 USA

A radiation hardened configuration bit cell design is proposed for an SRAM-based FPGA used in space application. The p-type gate poly on p-substrate structure provides a radiation immune resistor and a capacitor for RC hardened signal path. In addition to area efficiency, the proposed cell also overcomes the traditional linear energy transfer sensitivity to process and temperature variation.

关键词： Field programmable gate arrays Programmable logic devices gate array circuits Electric resistors Linear energy transfer Temperature Electric circuits

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Discrete Charge Storage Nonvolatile Memory Based on Si Nanocrystals with Nitridation Treatment

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Chinese Physics Letters 2010年第8期27卷 180-182页

作者：张贤高陈坤基方忠慧钱昕晔刘广元江小帆马忠元徐骏黄信凡计建新何飞宋矿宝张俊万辉王荣华 National Laboratory of Solid State Microstructures and Department of Physics Nanjing University Nanjing 210093 Wuxi China Resources Huajing Micro Electronics Co. Ltd. Wuxi 214061

A nonvolatile memory device with nitrided Si nanocrystals embedded in a floating gate was fabricated. The uniform Si nanocrystals with high density （3× 10^11 cm^-2 ） were deposited on ultra-thin tunnel oxide layer （- 3 nm） and followed by a nitridation treatment in ammonia to form a thin silicon nitride layer on the surface of nanocrystals. A memory window of 2.4 V was obtained and it would be larger than 1.3 V after ten years from the extrapolated retention data. The results can be explained by the nitrogen passivation of the surface traps of Si nanoerystals, which slows the charge loss rate.

关键词： COMPUTER storage devices ELECTRIC charge & distribution SILICON crystals NANOCRYSTALS NITRIDING gate array circuits DENSITY AMMONIA

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Extendable and dynamically reconfigurable multi-protocol firewall

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INTERNATIONAL JOURNAL OF SOFTWARE ENGINEERING AND KNOWLEDGE ENGINEERING 2005年第2期15卷 363-371页

作者： Ly, S Bigdeli, A Univ Auckland Dept Elect & Comp Engn Embedded Syst Res Grp Auckland 1 New Zealand

Security issues within a networking environment are critical, as attacks or intrusions can come from many different sources. Firewalls are an effective tool used for intrusion detection and provide protection against attacks on a system or network. In the past, protection barriers for a local network have been provided using software solutions. Emerging multi-gigabit networking technology and the high uptake of gigabit Ethernet has rendered these solutions inefficient as it cannot cope with the high data rate. In this paper, a new approach using reconfigurable hardware such as Field Programmable gate arrays is proposed to provide the flexibility and performance required for a gigabit firewall. The solution is extendable, has low cost and is capable of scanning multiple protocols. The design approach will allow it to be easily ported over to another family of chips with no or minor modification.

关键词： FIREWALLS (Computer security) COMPUTER network security COMPUTER security ETHERNET (Local area network system) FIELD programmable gate arrays gate array circuits PROGRAMMABLE logic devices

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Modeling and simulation for the enhancement of electron storage in a stacked multilayer nanocrystallite silicon floating gate memory

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JOURNAL OF APPLIED PHYSICS 2007年第1期102卷 014501-1-014501-6页

作者： Yu, L. W. Chen, K. J. Ding, H. L. Xu, J. Liu, K. Li, W. Wang, X. Huang, X. F. Nanjing Univ Natl Lab Solid State Microstruct Nanjing 210093 Peoples R China Nanjing Univ Dept Phys Nanjing 210093 Peoples R China

In this article, we investigate the storage enhancement mechanism of stacked multilayer nanocrystallite silicon (nc-Si) structures in a master-equation-based equivalent circuit model. As a theoretical extension from our previous experimental works, we reveal the detail injection sequence of electrons into the multilayer nc-Si structure via a direct tunneling process, and how the retention property is enhanced by the stacked structures. Seeking a further improvement in the multilayer nc-Si-based nonvolatile memory structure, we compare two major approaches for that purpose, i.e. (1) by further increasing the number of stacked layers or (2) by adopting an asymmetric double-layer structure. It is shown that the latter is more promising for achieving better nonvolatile storage property and shows a more effective threshold shifting, while retaining the virtues of direct tunneling process like fast write/erase and low operation voltage. We suggest that these results provide important guides for practical design of memory devices based on multilayer nc-Si floating gate structures. (c) 2007 American Institute of Physics.

关键词： TUNNELING (Physics) ELECTRIC conductivity NANOCRYSTALS SILICON FERROELECTRIC storage cells gate array circuits

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