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gate array Using Low-Temperature Poly-Si Thin-Film Transistors

IEICE TRANSACTIONS ON ELECTRONICS 2020年第7期E103C卷 341-344页

作者： Kimura, Mutsumi Inoue, Masashi Matsuda, Tokiyoshi Ryukoku Univ Dept Elect & Informat Otsu Shiga 5202194 Japan High Tech Res Ctr Innovat Mat & Proc Res Ctr Otsu Shiga 5202194 Japan

We have designed gate arrays using low-temperature poly-Si thin-film transistors and confirmed the correct operations. Various kinds of logic gates are beforehand prepared, contact holes are later bored, and mutual wiring is formed between the logic gates on demand. A half adder, two-bit decoder, and flip flop are composed as examples. The static behaviors are evaluated, and it is confirmed that the correct waveforms are output. The dynamic behaviors are also evaluated, and it is concluded that the dynamic behaviors of the gate array are less deteriorated than that of the independent circuit.

关键词： gate array low-temperature poly-Si (LTPS) thin-film transistor (TFT)

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Programmable a-InGaZnO gate array with laser-induced forward transfer

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FLEXIBLE AND PRINTED ELECTRONICS 2021年第1期6卷

作者： Jo, Youngmin Kwon, Jimin van der Steen, Jan-Laurens Kronemeijer, Auke Jisk Jung, Sungjune Pohang Univ Sci & Technol Dept Convergence IT Engn Pohang South Korea Stanford Univ Dept Elect Engn Stanford CA 94305 USA Holst Ctr TNO Eindhoven Netherlands Pohang Univ Sci & Technol Dept Mat Sci & Engn Pohang South Korea

Here, we present a pseudo-CMOS NOR gate array based on dual-gate amorphous indium-gallium-zinc oxide thin-film transistors (TFTs) on plastic. We fabricated a 14 x 12 array of NOR gates which was programmed using laser-induced forward transfer printing technology to realize a negative-edge-triggered D flip-flop. Two drive transistors in a conventional NOR gate configuration were replaced by a single independently gate-controlled dual-gate transistor, which enabled us to design and fabricate a gate array with much reduced number of transistors and interconnects. We anticipate that programmable gate arrays based on dual-gate oxide TFTs can be a new route to design and fabrication of digital circuitry that will be essential for emerging applications Internet-of-Things and wearable electronics.

关键词： gate array thin-film circuit fabrication metal oxide semiconductor printed electronics flexible

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A New High-Density 10T CMOS gate-array Base Cell for Two-Port SRAM Applications

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IEICE TRANSACTIONS ON ELECTRONICS 2016年第6期E99C卷 717-726页

作者： Shibata, Nobutaro Gotoh, Yoshinori Ishihara, Takako NTT Corp NTT Microsyst Integrat Labs Atsugi Kanagawa 2430198 Japan

Two-port SRAMs are frequently installed in gate-array VLSIs to implement smart functions. This paper presents a new high-density 10T CMOS base cell for gate-array-based two-port SRAM applications. Using the single base cell alone, we can implement a two-port memory cell whose bitline contacts are shared with the memory cell adjacent to one of two dedicated sides, resulting in greatly reduced parasitic capacitance in bitlines. To throw light on the total performance derived from the base cell, a plain two-port SRAM macro was designed and fabricated with a 0.35-mu m low cost, logic process. Each of two 10-bit power-saved address decoders was formed with 36% fewer base cells by employing complex gates and a subdecoder. The new sense amplifier with a complementary sensing scheme had a fine sensitivity of 35 mV(pp), and so we successfully reduced the required read bitline signal from 250 to 70 mV(pp). With the macro with 1024 memory cells per bitline, the address access time under typical conditions of a 2.5-V power supply and 25 degrees C was 4.0 ns (equal to that obtained with full-custom style design) and the power consumption at 200-MHz simultaneous operations of two ports was 6.7 mW for an I/O-data width of 1 bit.

关键词： 10T type bitline capacitance CMOS gate array high speed low power memory-oriented base cell shared contact two-port SRAM

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Radiation-hardened gate array with embedded SRAM 15

Radiation-hardened gate array with embedded SRAM

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2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS)

作者： Malashevich, N. Makarceva, M. Fedorov, R. Sci Mfg Complex Technol Ctr Moscow Russia Natl Res Univ Elect Technol MIET Moscow Russia

the problem of information storage reliability improvement in random access memory (RAM) devices oriented to application as part of gate arrays designed for space-related application is considered in this article.

ISBN: (纸本)9781509002320

关键词： RAM memory cell gate array radiation hardness

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High-Density RAM/ROM Macros Using CMOS gate-array Base Cells: Hierarchical Verification Technique for Reducing Design Cost

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2015年第8期23卷 1415-1428页

作者： Shibata, Nobutaro Gotoh, Yoshinori NTT Microsyst Integrat Labs Atsugi Kanagawa 2430198 Japan

A gate array has a great advantage in that the extra cost required for customizing VLSI masks is low and the lead time needed to obtain an ASIC is short. Hence, it is widely and generally used in the ASIC industry as a major semicustomized VLSI design methodology. This paper presents high-density RAM/ROM macros using memory-oriented CMOS gate-array base cells. The metatile methodology along with a hierarchical verification technique is used for macro design;all the interconnection wires needed to generate a RAM/ROM macro are installed in each physical leaf cell by way of preparation. The macro size is configurable regarding both word count and bit width. Moreover, back annotations after generating a macro are not necessary because there are no unknown factors such as parasitic resistance and/or capacitance. To reduce the power consumption of RAM/ROM macros, six narrow-channel MOSFETs (two pMOSs and four nMOSs) are prepared in the base cell, resulting in a new 10-transistor-type base cell. Using one single base cell, we can implement an SRAM cell (up to two ports), a 4-bit ROM cell, or a 2-input logic gate. When designing the ROM cell, we adopt a double-rail bitline scheme to shorten the bitline delay. Another high-speed technique is to use a new current-mirror sense amplifier. Owing to the high sensitivity (47 mV) of this amplifier, we have successfully reduced the required read bitline signal from 300 to 100 mVpp. With regards to layout techniques, we propose a new high-density address decoder using a subdecoder and complex logic gates. In addition, some verification techniques using phantom base cells are devised. These techniques are confirmed with a gate-array RAM/ROM macro test chip fabricated with a 0.6-mu m low cost, CMOS process. With a two-port SRAM with 256 cells/bitline, the address access time under typical conditions of 3.3 V and 25 degrees C is 7.125 ns and the power-supply current at a 40-MHz operation is 3.8 mA for an I/O-data width of 1 bit.

关键词： CMOS gate array hierarchical verification high density high speed low power macro memory-oriented base cell RAM ROM

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Formation of holographic memory for optically reconfigurable gate array by angle-multiplexing recording of multi-circuit information in liquid crystal composites

Formation of holographic memory for optically reconfigurable...

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Conference on Emerging Liquid Crystal Technologies IX

作者： Ogiwara, Akifumi Maekawa, Hikaru Watanabe, Minoru Moriwaki, Retsu Kobe City Coll Technol Dept Elect Engn Nishi Ku 8-3 Gakuen Higashi Kobe Hyogo 6512194 Japan Shizuoka Univ Fac Engn Dept Elect & Elect Engn Hamamatsu Shizuoka 4328561 Japan

ISBN: (纸本)9780819499172

A holographic polymer-dispersed liquid crystal (HPDLC) memory to record multi-context information for an optically reconfigurable gate array is formed by the angle-multiplexing recording using a successive laser exposure in liquid crystal (LC) composites. The laser illumination system is constructed using the half mirror and photomask written by the different configuration contexts placed on the motorized stages under the control of a personal computer. The fabricated holographic memory implements a precise reconstruction of configuration contexts corresponding to the various logical circuits such as OR circuit and NOR circuit by the laser illumination at different incident angle in the HPDLC memory.

关键词： holographic memory recording liquid crystal optically reconfiguration laser angle-multiplexing gate array multi-circuit

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Radiation-hardened gate array with embedded SRAM

Radiation-hardened gate array with embedded SRAM

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European Conference on Radiation and its Effects on Components and Systems

作者： N. Malashevich M. Makarceva R. Fedorov Scientific-Manufacturing Complex "Technological center" National Research University of Electronic Technology (MIET)

The problem of information storage reliability improvement in random access memory (RAM) devices oriented to application as part of gate arrays designed for space-related application is considered in this article.

ISBN: (纸本)9781509002337

关键词： RAM Memory cell gate array Radiation hardness

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Research on multiple classified signal detection algorithms based on mimo-ofdm system

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MICROPROCESSORS AND MICROSYSTEMS 2021年 81卷 103530-103530页

作者： He, Yali Liu, Yuchun Guo, Yanhua Zhang, Haihui ZhouKou Normal Univ Zhoukou 466001 Henan Peoples R China Zhoukou Vocat & Tech Coll Zhoukou 466001 Henan Peoples R China

OFDM is a high-speed signal transmission technology in wireless environment. In wireless channels, the frequency response curve is generally non-flat. MIMO technology can effectively increase system capacity, improve system performance, and improve network coverage and transmission reliability. OFDM technology can effectively resist intersymbol crosstalk caused by multipath propagation by adding a certain length of redundant guard interval in front of transmission symbols. According to the channel estimation and signal detection algorithms in MIMO?OFDM systems, this paper will choose a better algorithm to implement MIMO?OFDM systems and channel estimation and signal detection algorithms. Theoretical analysis and simulation results show that the optimal detection algorithm has the best performance, but its complexity is exponentially related to the number of antennas and modulation order. The architecture for dense texture analysis is developed based on Field Programmable gate array FPGA device which is a general engine for high-speed image processing. In order to maximize the performance, our architecture is designed for minimizing consumed resources. As explained in subsection our architecture is composed of two main operations, namely the AH based sum and difference of images and the calculus of texture features

关键词： MIMO-OFDM system Signal detection Channel estimation Signal detection algorithm field programmable gate array

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Functional ECO Using Metal-Configurable gate-array Spare Cells 14

Functional ECO Using Metal-Configurable Gate-Array Spare Cel...

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51st ACM/EDAC/IEEE Design Automation Conference (DAC)

作者： Chang, Hua-Yu Jiang, Iris Hui-Ru Chang, Yao-Wen Natl Taiwan Univ Grad Inst Elect Engn Taipei 10617 Taiwan Natl Chiao Tung Univ Dept Elect Engn & Inst Elect Hsinchu 30010 Taiwan Natl Taiwan Univ Dept Elect Engn Taipei 10617 Taiwan

ISBN: (纸本)9781450327305

Metal-configarable gate-array spare cells, which have versatile functionality, are developed to overcome the inflexibility of standard spare cells used in conventional metal-only engineering change order (ECO). In this paper, we focus on functional ECO optimization using the new type of spare cells to fully exploit its strength. We observe that this functional LCD problem has the nature of dynamic logical and physical costs for at spare gate arrays. Unlike existing functional E0 works, which perform technology snapping based on ECO patches, we perform reverse mapping from spare gate arrays to handle these dynamic costs. We devise a spare array relation graph to record geometrical adjacency among spare gate arrays and interleave with the and-inverter network of ECO patches. To avoid redundant traversal and monitor the dynamic costs, we adopt A* search to simultaneously traverse and imp between the logical LCD network and the physical spare array relation graph.

关键词： Engineering change order gate array Technology mapping

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ECO Optimization Using Metal-Configurable gate-array Spare Cells

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2013年第11期32卷 1722-1733页

作者： Chang, Hua-Yu Hui-Ru, Iris Chang, Yao-Wen Natl Taiwan Univ Grad Inst Elect Engn Taipei 10617 Taiwan Natl Chiao Tung Univ Dept Elect Engn Hsinchu 30010 Taiwan Natl Chiao Tung Univ Inst Elect Hsinchu 30010 Taiwan Natl Taiwan Univ Dept Elect Engn Taipei 10617 Taiwan Natl Taiwan Univ Grad Inst Elect Engn Taipei 10617 Taiwan Acad Sinica Res Ctr Informat & Technol Innovat Taipei 11529 Taiwan

Due to the rapidly increasing design complexity in modern IC designs, metal-only engineering change order (ECO) becomes inevitable to achieve design closure with a low respin cost. Traditionally, preplaced redundant standard cells are regarded as spare cells. However, these cells are limited by predefined functionalities and locations, and they always consume leakage power despite their inputs being tied off. To overcome the inflexibility and power overhead, a new type of spare cells, called metal-configurable gate-array spare cells, are introduced. In this paper, we address a new ECO problem, which performs design changes using metal-configurable gate-array spare cells. We first study the properties of this new ECO problem and propose a new cost metric, aliveness, to model the capability of a spare gate array. Based on aliveness and routability, we then develop two ECO optimization frameworks, one for timing ECO and the other for functional ECO. Experimental results show that our approach delivers superior efficiency and effectiveness.

关键词： Engineering change order gate array mixed integer linear programming

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