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Identifying Optimal Workload Offloading Partitions for CPU-PIM graph processing Accelerators

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第4期33卷 1053-1064页

作者： Xu, Sheng Li, Chun Luo, Le Zhou, Wu Yan, Liang Chen, Xiaoming Anhui Normal Univ Sch Comp & Informat Wuhu 241000 Anhui Peoples R China Inst Artificial Intelligence Hefei Comprehens Natl Sci Ctr Hefei 230088 Peoples R China Chinese Acad Sci Inst Comp Technol Beijing 100190 Peoples R China

The integrated architecture that features both in-memory logic and host processors, or so-called "processing-in-memory" (PIM) architecture, is an emerging and promising solution to bridge the performance gap between the memory and host processors. In spite of the considerable potential of PIM, the workload offloading policy, which partitions the program and determines where code snippets are executed, is still a main challenge in PIM. In order to determine the best PIM offloading partitions, existing methods require in-depth program profiling to create the control flow graph (CFG) and then transform it into a graph-cut problem. These CFG-based solutions depend on detailed profiling of a crucial element, the execution time of basic blocks, to accurately assess the benefits of PIM offloading. The issue is that these execution times can change significantly in PIM, leading to inaccurate offloading decisions. To tackle this challenge, we present a novel PIM workload offloading framework called "RDPIM" for CPU-PIM graph processing accelerators, which systematically considers the variations in the execution time of basic blocks. By analyzing the relationship between data dependencies among workloads and the connectivity of input graphs, we identified three key features that can lead to variations in execution time. We developed a novel reuse distance (RD)-based model to predict the exact performance of basic blocks for optimal offloading decisions. We evaluate RDPIM using real-world graphs and compare it with some state-of-the-art PIM offloading approaches. Experiments have demonstrated that our method achieves an average speedup of 2x compared to CPU-only executions and up to 1.6x compared to state-of-the-art PIM offloading schemes.

关键词： Program processors Logic Codes Arrays Runtime Electronic mail Accuracy Very large scale integration Training Through-silicon vias graph processing heterogenous systems processing-in-memory (PIM) reuse distance (RD) workload offloading

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PRAGA: A Priority-Aware Hardware/Software Co-design for High-Throughput graph processing Acceleration

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ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2025年第1期22卷 1-27页

作者： Zheng, Long Zhu, Bing Yao, Pengcheng Zhou, Yuhang Pan, Chengao Zhao, Wenju Liao, Xiaofei Jin, Hai Xue, Jingling Huazhong Univ Sci & Technol Natl Engn Res Ctr Big Data Technol & Syst Sch Comp Sci & Technol Serv Comp Technol & Cluster & Grid Comp LabSyst L Wuhan Hubei Peoples R China Univ New South Wales Sch Comp Sci & Engn Sydney NSW 2052 Australia

graph processing is pivotal in deriving insights from complex data structures but faces performance limitations due to the irregular nature of graphs. Traditional general-purpose processors often struggle with low instruction-level parallelism and energy inefficiency when handling graph data. In response, modern graph accelerators have embraced an intra-edge-parallel model to enhance parallelization, significantly outperforming conventional processors. However, the indiscriminate processing of edges in existing systems results in substantial computational redundancy, negatively impacting overall efficiency. This article introduces PRAGA, an innovative graph accelerator designed to optimize efficiency by selectively processing edges that significantly contribute to final results while preserving high computational parallelism. PRAGA utilizes an intra-edge-sequential model, prioritizing edge processing to capitalize on coarse-grained vertex-level parallelism and minimize unnecessary computations. It incorporates a hot-value manager to alleviate network-on-chip congestion and a memory-aware coalescer to minimize redundant data accesses. Our experimental results, obtained using a Xilinx Alveo U280 FPGA accelerator card, demonstrate that PRAGA achieves speedups of 17.88x and 5.86x over state-of-the-art accelerators Scalagraph and graphDyns, respectively, and outperforms the advanced GPU-based system Gunrock by 22.52x on average. This substantial improvement underscores PRAGA's potential to redefine performance benchmarks in graph processing.

关键词： graph processing accelerators priority-aware redundancy parallelism

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Towards Communication-Efficient Out-of-Core graph processing on the GPU

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2025年第5期36卷 961-976页

作者： Wang, Qiange Ai, Xin Yan, Yongze Gong, Shufeng Zhang, Yanfeng Chen, Jing Yu, Ge Northeastern Univ Sch Comp Sci & Engn Shenyang 110819 Peoples R China

The key performance bottleneck of large-scale graph processing on memory-limited GPUs is the host-GPU graph data transfer. Existing GPU-accelerated graph processing frameworks address this issue by managing the active subgraph transfer at runtime. Some frameworks adopt explicit transfer management approaches based on explicit memory copy with filter or compaction. In contrast, others adopt implicit transfer management approaches based on on-demand accesses with the zero-copy mechanism or unified virtual memory. Having made intensive analysis, we find that as the active vertices evolve, the performance of the two approaches varies in different workloads. Due to heavy redundant data transfers, high CPU compaction overhead, or low bandwidth utilization, adopting a single approach often results in suboptimal performance. Moreover, these methods lack effective cache management methods to address the irregular and sparse memory access pattern of graph processing. In this work, we propose a hybrid transfer management approach that takes the merits of both two transfer approaches at runtime. Moreover, we present an efficient vertex-centric graph caching framework that minimizes CPU-GPU communication by caching frequently accessed graph data at runtime. Based on these techniques, we present Hytgraph, a GPU-accelerated graph processing framework, which is empowered by a set of effective task-scheduling optimizations to improve performance. Experiments on real-world and synthetic graphs show that Hytgraph achieves average speedups of 2.5 x, 5.0 x, and 2.0 x compared to the state-of-the-art GPU-accelerated graph processing systems, Grus, Subway, and EMOGI, respectively.

关键词： graphics processing units Public transportation Memory management Iterative methods Data transfer Costs Runtime Partitioning algorithms Bandwidth Parallel processing GPU graph processing communication reduction transfer management out-of-core processing

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SGgraph: A Scalable GPU-Based Edge-Centric graph processing Framework

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INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2025年第3期53卷 1-32页

作者： Yakhlef, Ala Eddine Yahiaoui, Said Bendjoudi, Ahcene Ecole Natl Super Informat ESI BP M68Oued Smar Algiers 16270 Algeria CERIST Ctr Rech Informat Sci & Tech Ben Aknoun Algiers 16030 Algeria

In today's interconnected world, data is often represented as graphs due to their ability to capture relationships between data entities. Recently, graph processing has gained significant interest in both academia and industry because it enables the extraction of valuable insights from these graphs. Due to their massive parallelism at a lower cost, GPUs have become the preferred choice for graph processing. However, fully exploiting the power of GPUs for graph processing is challenging due to the irregular nature of graphs, which is incompatible with GPU architecture. To address this challenge and facilitate the development of graph algorithms on GPUs, several graph processing frameworks have been developed. However, most current GPU graph processing frameworks struggle to handle real-world graphs because their size often exceeds the memory capacity of GPUs. Additionally, the preprocessing phase required by most frameworks often dominates the total execution time. In this paper, we propose SGgraph, a scalable GPU-based graph processing framework that makes graph computation compatible with GPU architecture without the need for preprocessing. Our framework can handle large graphs that do not fit in GPU memory and can process graphs with billions of edges on a single machine using multiple GPUs. Our experiments show that SGgraph outperforms existing GPU-based frameworks, achieving competitive processing time and remarkable reductions in total execution time, with improvements averaging a factor of 7.7 to 19.7.

关键词： graph processing Edge-centric Topology-driven CUDA streams Multi-GPU

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Nezha: An Efficient Distributed graph processing System on Heterogeneous Hardware

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Proceedings of the ACM on Management of Data 2025年第1期3卷 1-27页

作者： Pengjie Cui Haotian Liu Dong Jiang Bo Tang Ye Yuan Northeastern University Shenyang China Southern University of Science and Technology Shenzhen China Southern University of Science and Technology Shenzhen Guangzhou China Beijing Institute of Technology Beijing China

The growing scale of graph data across various applications demands efficient distributed graph processing systems. Despite the widespread use of the Scatter-Gather model for large-scale graph processing across distributed machines, the performance still can be significantly improved as the computation ability of each machine is not fully utilized and the communication costs during graph processing are expensive in the distributed environment. In this work, we propose a novel and efficient distributed graph processing system Nezha on heterogeneous hardware, where each machine is equipped with both CPU and GPU processors and all these machines in the distributed cluster are interconnected via Remote Direct Memory Access (RDMA).To reduce the communication costs, we devise an effective communication mode with a graph-friendly communication protocol in the graph-based RDMA communication adapter of Nezha. To improve the computation efficiency, we propose a multi-device cooperative execution mechanism in Nezha, which fully utilizes the CPU and GPU processors of each machine in the distributed cluster. We also alleviate the workload imbalance issue at inter-machine and intra-machine levels via the proposed workload balancer in Nezha. We conduct extensive experiments by running 4 widely-used graph algorithms on 5 graph datasets to demonstrate the superiority of Nezha over existing systems.

关键词： graph processing heterogeneous hardware

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ACgraph: Accelerating Streaming graph processing via Dependence Hierarchy 23

ACGraph: Accelerating Streaming Graph Processing via Depende...

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Proceedings of the 60th Annual ACM/IEEE Design Automation Conference

作者： Zihan Jiang Fubing Mao Yapu Guo Xu Liu Haikun Liu Xiaofei Liao Hai Jin Wei Zhang National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China Department of Electronic and Computer Engineering HKUST Hong Kong

ISBN: (纸本)9798350323481

Streaming graph processing needs to timely evaluate continuous queries. Prior systems suffer from massive redundant computations due to the irregular order of processing vertices influenced by updates. To address this issue, we propose ACgraph, a novel streaming graph processing approach for monotonic graph algorithms. It maintains dependence trees during runtime, and makes affected vertices processed in a top-to-bottom order in the hierarchy of the dependence trees, thus normalizing the state propagation order and coalescing of multiple propagation to the same vertices. Experimental results show that ACgraph reduces the number of updates by 50% on average, and achieves the speedup of 1.75~7.43× over state-of-the-art systems.

关键词： graph processing

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graph processing and machine learning architectures with emerging memory technologies: a survey

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Science China(Information Sciences) 2021年第6期64卷 5-29页

作者： Xuehai QIAN Ming Hsieh Department of Electrical and Computer Engineering University of Southern California

This paper surveys domain-specific architectures(DSAs) built from two emerging memory technologies. Hybrid memory cube(HMC) and high bandwidth memory(HBM) can reduce data movement between memory and computation by placing computing logic inside memory dies. On the other hand, the emerging non-volatile memory, metal-oxide resistive random access memory(ReRAM) has been considered as a promising candidate for future memory architecture due to its high density, fast read access and low leakage power. The key feature is ReRAM's capability to perform the inherently parallel in-situ matrixvector multiplication in the analog domain. We focus on the DSAs for two important applications—graph processing and machine learning acceleration. Based on the understanding of the recent architectures and our research experience, we also discuss several potential research directions.

关键词： graph processing machine learning acceleration ReRAM HMC/HBM

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graph processing on GPUs: A Survey

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ACM COMPUTING SURVEYS 2018年第6期50卷 1–35页

作者： Shi, Xuanhua Zheng, Zhigao Zhou, Yongluan Jin, Hai He, Ligang Liu, Bo Hua, Qiang-Sheng Huazhong Univ Sci & Technol Sch Comp Sci & Technol Serv Comp Technol & Syst Lab Big Data Technol & Syst Lab 1037Luoyu Rd Wuhan Hubei Peoples R China Univ Copenhagen Dept Comp Sci Univ Pk 5 DK-2100 Copenhagen Denmark Univ Warwick Dept Comp Sci Coventry CV4 7AL W Midlands England

In the big data era, much real-world data can be naturally represented as graphs. Consequently, many application domains can be modeled as graph processing. graph processing, especially the processing of the large-scale graphs with the number of vertices and edges in the order of billions or even hundreds of billions, has attracted much attention in both industry and academia. It still remains a great challenge to process such large-scale graphs. Researchers have been seeking for new possible solutions. Because of the massive degree of parallelism and the high memory access bandwidth in GPU, utilizing GPU to accelerate graph processing proves to be a promising solution. This article surveys the key issues of graph processing on GPUs, including data layout, memory access pattern, workload mapping, and specific GPU programming. In this article, we summarize the state-of-the-art research on GPU-based graph processing, analyze the existing challenges in detail, and explore the research opportunities for the future.

关键词： graph processing GPU graph datasets parallelism BSP model GAS model

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graph processing Scheme Using GPU With Value-Driven Differential Scheduling

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IEEE ACCESS 2024年 12卷 41590-41600页

作者： Song, Sangho Lee, Hyeonbyeong Kim, Yuna Lim, Jongtae Choi, Dojin Bok, Kyoungsoo Yoo, Jaesoo Chungbuk Natl Univ Dept Informat & Commun Engn Cheongju 28644 Chungcheongbuk South Korea Chungbuk Natl Univ Dept Big Data Cheongju 28644 Chungcheongbuk South Korea Changwon Natl Univ Dept Comp Engn Changwon Si 51140 Gyeongsangnam D South Korea Wonkwang Univ Dept Software Convergence Iksan Si 54538 Jeollabuk Do South Korea

Researchers have recently been using GPUs to process large quantities of graph data. However, the challenges in Host-GPU data transfer must be addressed to effectively use GPUs for graph processing. Although existing frameworks have attempted to mitigate this problem by managing active graph data transfers, issues persist owing to the need to divide graphs into subgraphs for parallel processing across multiple GPU cores. This division often leads to duplicated data transfers, resulting in high transmission overhead and low bandwidth utilization. To address these challenges and expedite graph computation, this study proposes a graph processing scheme using a GPU with value-driven differential scheduling. This approach involves dividing large graphs into subgraphs of similar sizes and contiguous vertices, allowing efficient parallelization on the GPU. The value of each subgraph is assessed based on its activity level, and its computation load is estimated using a differential subgraph scheduling technique. The proposed scheme distinguishes between high-value and low-value subgraphs and allocates them to different graph processing engines. This reduces the redundant data transmissions and enhances the transmission rate of active edges, thereby reducing the Host-GPU data transmission overhead. Experimental results demonstrate that the proposed scheme achieves a notable speedup of up to 6.6 times compared to the existing GPU-accelerated graph processing systems, including graphCage and Subway.

关键词： GPU graph processing graph partitioning

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An effective framework for asynchronous incremental graph processing

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Frontiers of Computer Science 2019年第3期13卷 539-551页

作者： Xinqiao LV Wei XIAO Yu ZHANG Xiaofei LIAO Hai JIN Qiangsheng HUA Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan 430074 China

Although many graph processing systems have been proposed, graphs in the real-world are often dynamic. It is important to keep the results of graph computation up-todate. Incremental computation is demonstrated to be an efficient solution to update calculated results. Recently, many incremental graph processing systems have been proposed to handle dynamic graphs in an asynchronous way and are able to achieve better performance than those processed in a synchronous way. However, these solutions still suffer from sub-optimal convergence speed due to their slow propagation of important vertex state (important to convergence speed) and poor locality. In order to solve these problems, we propose a novel graph processing framework. It introduces a dynamic partition method to gather the important vertices for high locality, and then uses a priority-based scheduling algorithm to assign them with a higher priority for an effective processing order. By such means, it is able to reduce the number of updates and increase the locality, thereby reducing the convergence time. Experimental results show that our method reduces the number of updates by 30%, and reduces the total execution time by 35%, compared with state-of-the-art systems.

关键词： incremental computation graph processing iterative computation asynchronous convergence

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