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2017 International Artificial Intelligence and Data Processing Symposium (IDAP)

作者： Isik, Ibrahim Tagluk, Mehmet Emin Inonu Univ Dep Elect Elect Engn Malatya Turkey

ISBN: (纸本)9781538618806

BER (bit error rate) measurement is an important criterion to analyze digital communication systems. In literature this measurement generally performed through simulation programs like Matlab/Simulink. It is considered that the simulation programs may not represent a real communication system and also they are quite time consuming and expensive. However, modeling communication systems with parallel processing and fast modules such as FPGA (Field Programmable Gate Arrays) using Vhdl (Very High Speed Integrated Circuit Hardware Description Language) and performing BER measurements on this modules is much faster, closer to the reality. The main interest of this study is to demonstrate the performance of FPGA based models in communication systems and show their advantages and disadvantages compared to the simulator models. Despite the simple structure of FPGA it sometimes restricts a complete design of the system because of comprising only gates, logic operators, register etc. Simulator models such as the ones designed with Matlab have a huge library which provides flexibility in the design and analysis of the system. Software and hardware developers try to develop new ways such as hdl coder and System Generator tools to get over these restrictions. But both methods still have some restrictions to design a better communication system. In this paper also this restrictions are investigated detailed. As an example, QPSK (Quadrature Phase Shift Keying) modulation is shown by using System Generator tool in this paper.

关键词： FPGA QPSK Modulation Vhdl hdl coder System Generator

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FPGA Implementation of Range Migration Algorithm for Synthetic Aperture Radar Using Simulink hdl coder

FPGA Implementation of Range Migration Algorithm for Synthet...

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IEEE International Symposium on Antennas and Propagation / INC/USNC-URSI Radio Science Meeting (AP-S/INC-USNC-URSI)

作者： Meng, Yang Yang, Haoyi Chen, Bocheng Chen, Guoping Qing, Anyong Chongqing Univ Posts & Telecommun Sch Optoelect Engn Chongqing 400065 Peoples R China Southwest Jiaotong Univ Sch Elect Engn Chengdu 611756 Peoples R China

ISBN: (纸本)9798350369908;9798350369915

The millimeter-wave synthetic aperture radar echo data processing is a vital step in target reconstruction, and this phase is inherently time-consuming, demanding significant computational resources. To expedite the reconstruction process, Field-Programmable Gate Arrays (FPGA) can be employed. Nevertheless, utilizing FPGA for implementation often entails grappling with complex hardware description languages such as Verilog or Vhdl, which are difficult and time-consuming to develop. To overcome these challenges, a hardware architecture based on the range migration algorithm (RMA) is proposed in this paper. We utilize the Simulink hdl coder toolbox to encapsulate the algorithm into an IP Core, subsequently verifying it on the Xilinx XC7Z020. The test results show that operating at a clock frequency of 100MHz, target reconstruction with original data of size 256x151x64 requires approximately 26.74 ms. This represents a notable acceleration, being about 7.2 times faster than CPU processing in Matlab.

关键词： FPGA RMA fast Fourier transform (FFT) synthetic aperture radar (SAR) Simulink hdl coder

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The Prognosis of Epilepsy with Naive Bayes Classifier On FPGA Using hdl coder

The Prognosis of Epilepsy with Naive Bayes Classifier On FPG...

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IEEE-EMBS Conference on Biomedical Engineering and Sciences (IECBES) - Leading Modern Healthcare Technology Enhancing Wellness

作者： Memon, Nauman Zaidi, Syyed Sajjad Haider Suleman, Muhammad Natl Univ Sci & Technol Dept Elect & Power Engn Islamabad Pakistan

ISBN: (纸本)9781728142456

Epilepsy is one of the serious neurological disorder that affects about 50 million individuals globally at all ages and that can be detected from electroencephalogram (EEG) signals. This paper discusses the implementation of the Naive Bayes' classifier for the classification of epileptic events into seizure or non-seizure class. The design is carried out in Simulink environment where as it's implementation is performed on qkintex-7 FPGA hardware using hdl coder. The fixed point tool of the MATLAB is used for the conversion of floating point data into fixed point to make the hardware implementation possible. This classification is performed in real time with approximately 95 % to 100% classification accuracy.

关键词： NBC FPGA hdl coder VLSI technology CVA RMS EEG CM

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OFDM based DVB-T System Implementation Using MATLAB and hdl coder

OFDM based DVB-T System Implementation Using MATLAB and HDL ...

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International Conference on Computing Methodologies and Communication (ICCMC)

作者： Pasha, Syed Gilani Kohir, Vinayadatt V. Visvesvaraya Technol Univ Belgaum India PDA Coll Engn Dept ECE Gulbarga Karnataka India

ISBN: (纸本)9781509048908

Digital Video Broadcast-Terrestrial (DVB-T) is a most extensively use standard for terrestrial TV transmission in the world. The OFDM has advantages of high spectral efficiency and inherent robustness against channel fading so it is used in DVB-T system. The BER performance of the DVB-T in 2K mode for 4-QAM constellations under AWGN, Rayleigh and Rician channel models is analyzed. In this research work, DVB-T system is implemented first using MATLAB and then the MATLAB code is converted into Vhdl code using hdl coder according to European telecommunications standards institute (ETSI), EN 300 744 standard. Synthesis and Simulation of OFDM based DVB-T in 2K mode have been carried out using Xilinx tool.

关键词： DVB-T OFDM Vhdl hdl coder QAM BER

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Cardiac Excitation Modeling: hdl coder Optimization towards FPGA stand-alone Implementation 4

Cardiac Excitation Modeling: HDL Coder Optimization towards ...

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4th IEEE International Conference on Control System Computing and Engineering (ICCSCE 2014)

作者： Othman, Norliza Mahmud, Farhanahani Mahamad, Abd Kadir Jabbar, M. Hairol Adon, Nur Atiqah Univ Tun Hussein Onn Malaysia UTHM Fac Elect & Elect Engn Batu Pahat Johor Malaysia UTHM Microelect & Nanotechnol Shamsuddin Res Ctr MiNT Cardiol & Physiome Anal Res Lab Batu Pahat Johor Malaysia UTHM Microelect & Nanotechnol Shamsuddin Res Ctr MiNT Manycore Syst Chip MCSoC Res Lab Batu Pahat Johor Malaysia

ISBN: (纸本)9781479956869

The aim of this paper is to discuss the optimization of the hardware description language (hdl) design using fixed-point optimization and speed optimization through a pipelining method. This optimization is very crucial to achieve the best performance in terms of speed, area and power consumption of the generated hdl code before deploying the field programmable gate array (FPGA) stand-alone implementation. As computational mathematical modeling needs immense amounts of simulation time, FPGA could bring the solutions as it provides high performance, and able to perform real-time simulations and compute in parallel mode operation. In this study, in order to ease verification, prototyping, and implementation FPGA, rapid prototyping model-based design approach of hdl coder from MathWorks has been used to automate hdl codes generation from a designed MATLAB Simulink blocks of Luo-Rudy Phase I (LR-I) model towards FPGA hardware-implemented for numerical solutions of ordinary differential equations (ODEs) responsible in generating the action potential (AP) waveform of mammalian cardiac ventricle cell. By using hdl coder, the model is successfully converted into an optimal fixed-point Vhdl design and the operating frequency is increased from 9.819 MHz to 23. 613MHz by pipelining optimization.

关键词： FPGA hardware-implemented cardiac excitation modeling Luo-Rudy Phase-I model hdl coder fixed-point optimization pipelining optimization

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Accelerating Video and Image Processing Design for FPGA using hdl coder and Simulink

Accelerating Video and Image Processing Design for FPGA usin...

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IEEE Conference on Sustainable Utilization and Development in Engineering and Technology (CSUDET)

作者： Hai, Jerry Chan Ting Pun, Ooi Chee Haw, Tan Wooi Multimedia Univ Fac Engn Cyberjaya 63100 Malaysia

ISBN: (纸本)9781479986125

Video and Image Processing solution requiring high throughput rate are often implemented in a dedicated hardware such as FPGA. The design process traditionally uses Verilog and Vhdl for synthesizing and validating the hardware. These design process are technically complex and time consuming. In this paper, we present an alternative approach using a model based design framework based on hdl coder, Vision hdl Toolbox and Simulink to accelerate the design of video and image solution. Several important issues in this framework are discussed namely, Pixel Streaming Design, Co-simulation and FPGA in the Loop (FIL). Based on this framework, a video of human walking are processed to extract out two features which are the human height and edge. The design is implemented in an Altera DE2-115 FPGA board. The goal of this paper is to tackle the technical complexity and reduce development time of traditional FPGA design.

关键词： FPGA video processing hdl coder Simulink Vision hdl Toolbox Model Based Design Co-Simulation FPGA in the Loop Pixel Streaming Design feature extraction

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RAPID PROTOTYPING OF PREDICTIVE DIRECT CURRENT CONTROL IN A LOW-COST FPGA USING hdl coder

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INTERNATIONAL JOURNAL OF POWER AND ENERGY SYSTEMS 2023年第10期43卷 1页

作者： Sankar, Deepa Lakshmi, S. Babu, C. A. Mathew, K. Cochin Univ Sci & Technol Div Elect Engn Kochi 682022 India APJ Abdul Kalam Technol Univ Mar Athanasius Coll Engn Kothamangalam 686666 India

This paper discusses a simple and efficient rapid prototyping method for the field programmable gate array (FPGA) implementation of computationally intensive finite state-predictive direct current control (FS-PDCC). The MATLAB/Simulink hardware description language (hdl) coder generates optimised Verilog code from hdl-supported Simulink blocks to fit a low-cost target-Intel Altera MAX((R)) 10 FPGA. The proposed work exhibits an efficient resource utilisation of the FPGA with an excellent cost-performance trade-off. In addition, the implemented control algorithm shows superior output quality, validated in Simulink, and verified experimentally in a two-level three-phase voltage source inverter (VSI) prototype. This approach will assist the power electronic designers to implement complex control algorithms rapidly and efficiently without manual coding, reducing the design productivity gap.

关键词： FPGA FS-PDCC model predictive control (MPC) hdl coder ADC IP core

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Enabling Model-Based Design for Real-Time Spike Detection

IEEE OPEN JOURNAL OF ENGINEERING IN MEDICINE AND BIOLOGY

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IEEE OPEN JOURNAL OF ENGINEERING IN MEDICINE AND BIOLOGY 2025年 6卷 312-319页

作者： Di Florio, Mattia Bornat, Yannick Care, Marta Cota, Vinicius Rosa Buccelli, Stefano Chiappalone, Michela Univ Genoa Dept Informat Bioengn Robot Syst Engn DIBRIS I-16145 Genoa Italy Univ Bordeaux Lab Integrat Mat Syst IMS Bordeaux INP CNRS UMR 5218 F-33405 Talence France IRCCS Osped Policlin San Martino I-16132 Genoa Italy Ist Italiano Tecnol Rehab Technol Lab I-16163 Genoa Italy

Goal: This study addresses the inherent difficulties in the creation of neuroengineering devices for real-time neural signal processing, a task typically characterized by intricate and technically demanding processes. Beneath the substantial hardware advancements in neurotechnology, there is often rather complex low-level code that poses challenges in terms of development, documentation, and long-term maintenance. Methods: We adopted an alternative strategy centered on Model-Based Design (MBD) to simplify the creation of neuroengineering systems and reduce the entry barriers. MBD offers distinct advantages by streamlining the design workflow, from modelling to implementation, thus facilitating the development of intricate systems. A spike detection algorithm has been implemented on a commercially available system based on a Field-Programmable Gate Array (FPGA) that combines neural probe electronics with configurable integrated circuit. The entire process of data handling and data processing was performed within the Simulink environment, with subsequent generation of hardware description language (hdl) code tailored to the FPGA hardware. Results: The validation was conducted through in vivo experiments involving six animals and demonstrated the capability of our MBD-based real time processing (latency <= 100.37 s) to achieve the same performances of offline spike detection. Conclusions: This methodology can have a significant impact in the development of neuroengineering systems by speeding up the prototyping of various system architectures. We have made all project code files open source, thereby providing free access to fellow scientists interested in the development of neuroengineering systems.

关键词： Hardware design languages Software packages Codes Field programmable gate arrays Computer architecture Hardware Signal processing algorithms Neural engineering Signal processing Computational modeling in vivo experiments hdl coder Field-Programmable Gate Array (FPGA) neuroengineering

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FPGA based hardware and device-independent implementation of chaotic generators

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AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2017年 82卷 211-220页

作者： Senouci, Abdelkader Bouhedjeur, Hamza Tourche, Kamal Boukabou, Abdelkrim Northumbria Univ Dept Comp & Informat Sci Pandon Bldg Newcastle Upon Tyne NE4 9XL Tyne & Wear England ESACH Dept Elect Algiers 16000 Algeria Jijel Univ Dept Elect Jijel 18000 Algeria

In this paper we will describe the use of Matlab/Simulink without third party toolboxes as a single integrated environment to study and generate the hdl description of chaotic systems for rapid prototyping purposes. We will provide a review of different approaches to implement chaos generators in both analog and digital forms with a focus on digital one. We will present a rapid prototyping method of digital chaos generators on FPGAs that is of great use for a seamless study, simulation and implementation of those systems in one environment. This will ease the design phase of the chaotic systems and will provide more flexibility for their study. Multiple chaos generators, such as Lorenz, Rossler, Chua, Linz-Sprott, and Sprott types have been designed using this method to showcase its effectiveness. In addition, for a better investigation of the chaotic dynamics, this work makes use of an implementation scheme that permits the visualization of the 3D chaotic attractor on the oscilloscope. The main focus of this paper is to provide a common implementation framework of chaos generators to target various applications, mainly cryptographic one. Newcomers to the field will easily dive in and active researchers will be able to speak the same language and build upon one anothers works more efficiently by adopting the presented guidelines. (C) 2017 Elsevier GmbH. All rights reserved.

关键词： Chaos Euler method Fixed-point FPGA hdl coder ODE Runge-Kutta

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Hardware implementation of neural network-based engine model using FPGA

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ALEXANDRIA ENGINEERING JOURNAL 2022年第12期61卷 12039-12050页

作者： Saady, Marina Magdy Essai, Mohamed Hassan Higher Inst Engn & Technol Elect & Commun Engn Dept Luxor Egypt Al Azhar Univ Fac Engn Qena Elect Engn Dept Cairo Egypt

This paper implements an artificial neural network (ANN)-based engine model using the Field Programmable Gate Array (FPGA). The developed (ANN)-based engine model will be used to estimate the engine gas emissions to mitigate the harmful effects of these emissions on human health. Getting reliable and robust FPGA-based ANNs implementations depends on the optimal choice of activation function that will provide minimal area occupation on FPGA. This study introduces, implements, and investigates FPGA-based ANN-based engine models using five different activation functions. These implemented engine models were described using MATLAB/Simulink and hardware description language coder and carried out by Spartan -***132 FPGA platform from Xilinx. The performance of the implemented engine models was investigated in terms of area-efficient implementation and the regression values (R) to build a robust ANN-based engine model.(c) 2022 THE AUTHORS. Published by Elsevier BV on behalf of Faculty of Engineering, Alexandria University This is an open access article under the CC BY-NC-ND license (http://***/ licenses/by-nc-nd/4.0/).

关键词： ANN hdl coder Engine emissions FPGA Back-propagation Activation function

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