This paper presents the digital implementation of fractional-order (FO) chaotic systems on Field Programmable Gate Array (FPGA). In the proposed work Simulink model of each chaotic system is first realized using hdl c...
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This paper presents the digital implementation of fractional-order (FO) chaotic systems on Field Programmable Gate Array (FPGA). In the proposed work Simulink model of each chaotic system is first realized using hdl coder of MATLAB, wherein each coefficient and signal is represented using a fixed number of bits. The construced design is translated into Vhdl code using hardware generation block. This code is further translated into bitstream file using Quartus software. The chaotic system is implemented by downloading the obtained bitstream file into Altera FPGA Cyclone IV E (EP4CE11529C7N) chip. A methodology has been developed to construct FO chaotic system using hdl coder. Five different FO chaotic systems, viz., Lorenz, Chen, Lu, Arneodo, and Lorenz Hyperchaotic system have been presented in the paper to illustrate the methodology. The systems have been implemented on FPGA platform. Analysis of each chaotic system is carried out on the basis of hardware resource utilization, static power analysis and synthesis frequency on FPGA. The results show that FPGA provides high-speed realizations with the desired accuracy and low power consumption for FO chaotic systems. (C) 2017 Elsevier GmbH. All rights reserved.
The development of communication networks has made information security more important than ever for both transmission and storage. Since the majority of networks involve images, image security is becoming a difficult...
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The development of communication networks has made information security more important than ever for both transmission and storage. Since the majority of networks involve images, image security is becoming a difficult challenge. In order to provide real-time image encryption and decryption, this study suggests an FPGA implementation of a video cryptosystem that has been well -optimized based on high level synthesis. The MATLAB hdl coder and Vivado Tools from Xilinx are used in the design, implementation, and validation of the algorithm on the Xilinx Zynq FPGA platform. Low resource consumption and pipeline processing are well -suited to the hardware architecture. For real-time applications involving secret picture encryption and decryption, the suggested hardware approach is widely utilized. This study suggests an implementation of the encryption -decryption system that is both very efficient and areaoptimized. A unique high-level synthesis (HLS) design technique based on application -specific bit widths for intermediate data nodes was used to realize the proposed implementation. For HLS, MATLAB hdl coder was used to generate register transfer level RTL design. Using Vivado software, the RTL design was implemented on the Xilinx ZedBoard, and its functioning was tested in real time using an input video stream. The results produced are faster and more are a efficient (target FPGA has fewer gates than before) than those of earlier solutions for the same target board.
Recently, with the development of technology and the lucubrate of automation technology, the dependence of modern industry on synchronous motors has gone deep into the bone. In fact, the current complex control algori...
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ISBN:
(纸本)9781665435765
Recently, with the development of technology and the lucubrate of automation technology, the dependence of modern industry on synchronous motors has gone deep into the bone. In fact, the current complex control algorithms consume the computing power of the data processing chips and put forward a higher request to the ability of developers. Therefore, the emphasis of this study lies in a rapid deployment method of a brushless DC motor servo control system based on the model methods. After using Simulink software to simulate and verify the three-closed-loop servo model of the DC brushless motor, Verilog or Vhdl language code will be generated, which can automatically configure the project according to the requirements. Moreover, a drive and control hardware platform based on Xilinx Zynq-7000 chips was built to verify the feasibility, the experimental results indicate that the proposed method can effectively simplify the deployment of complex algorithm codes, reduce the development cycle of brushless DC motor servo system with strong engineering practicability.
This paper describes the development of a prototype non-volatile FPGA space vector pulse width modulated digital controller for 3-level inverter. Algorithm for digital controller is first realized using simulink block...
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ISBN:
(纸本)9781538649961
This paper describes the development of a prototype non-volatile FPGA space vector pulse width modulated digital controller for 3-level inverter. Algorithm for digital controller is first realized using simulink blocks from hdl coder library of matlab. hdl coder transforms simulink model to fine and synthesizable very high speed integrated circuit hardware description language. Synthesis and execution tools generate bit stream of the code and it is executed to flash memory of FPGA. The developed prototype FPGA digital controller is validated on a 3-level inverter that energize three-phase open-end winding induction motor. Excellent harmonic performance is observed in real time spectral analysis of phase voltage and current of the motor. This development technique enables engineers to construct, simulate, authenticate and develop advanced schemes within small duration of time.
This paper describes rapid development technique of prototype non-volatile FPGA space vector pulse width modulated digital controller for a 3-level inverter. Control algorithm is first realized using simulink blocks o...
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ISBN:
(纸本)9781538660294
This paper describes rapid development technique of prototype non-volatile FPGA space vector pulse width modulated digital controller for a 3-level inverter. Control algorithm is first realized using simulink blocks of matlab. hdl coder converts simulink model to fine and synthesizable hardware description language. Bit stream corresponding to the code executed to flash memory of FPGA. The developed prototype FPGA digital controller is validated on a 3-level inverter that drives three-phase induction motor. The scheme is also verified with the DSP processor based dSPACE controller and compared its performance with that of developed controller. Excellent harmonic performance with very low total harmonic distortion and high spectral purity is observed for developed controller. This development technique enables engineers to construct, simulate and build advanced schemes within small duration of time.
In this paper, we propose a different approach from the traditional design flow by suggesting the use of model-based design tools provided by Matlab Simulink. The first contribution of our paper is the detailed defini...
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ISBN:
(纸本)9798350388978;9798350388961
In this paper, we propose a different approach from the traditional design flow by suggesting the use of model-based design tools provided by Matlab Simulink. The first contribution of our paper is the detailed definition of the model-based design approach and the design process. Another contribution of our paper involves the thorough examination and validation of software and hardware integration processes on the Vivado and Vitis platforms for the designed visual cryptography model, following the automatic code generation using hdl coder and Embedded coder tools.
This paper presents an ANFIS (adaptive neurofuzzy inference system) controller for a teleoperation system using FPGA (Field Programmable Gate Array). The proposed controller allows adapting to the dynamic variations o...
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ISBN:
(纸本)9781728109336
This paper presents an ANFIS (adaptive neurofuzzy inference system) controller for a teleoperation system using FPGA (Field Programmable Gate Array). The proposed controller allows adapting to the dynamic variations of the master and slave models by adjusting the output parameters of the neuro-fuzzy network using a learning algorithm, while taking advantage of the benefits of the FPGA computing power and its high sampling frequency. The ANFIS controllers are developed in MAT LAB-Simulink environment and implemented using Simulink's Fixed point tool and hdl coder. These features provide a fast and accurate control algorithm while optimizing the hardware resources used by the FPGA. The proposed controllers are implemented on a teleoperation system with one degree of freedom. The experimental position tracking results clearly show that the proposed control algorithm guarantees better performance compared to conventional control methods (PID).
The ubiquity and flexibility of 5G networks make it an attractive technology to customize for particular needs. In this work, we highlight some of the challenges associated with implementing custom 5G applications in ...
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ISBN:
(纸本)9798350308600
The ubiquity and flexibility of 5G networks make it an attractive technology to customize for particular needs. In this work, we highlight some of the challenges associated with implementing custom 5G applications in hardware and the growing trend of utilizing high-level synthesis tools to relieve these issues. We present an overview of the 5G resource grid and the MATLAB-Simulink-hdl coder workflow. We then demonstrate the workflow through an example 5G resource grid transmitter design.
The aim from this work is to invest the interest of using hardware solutions such as FPGAs for the digital implementation of control algorithms of Power factor correction converter. For this reason, a methodical appro...
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ISBN:
(纸本)9781728120539
The aim from this work is to invest the interest of using hardware solutions such as FPGAs for the digital implementation of control algorithms of Power factor correction converter. For this reason, a methodical approach based on an appropriate design methodology is firstly presented and discussed. An FPGA in the loop control for the PFC was done using Matlab, Altera Quartus II, and Altera DE1-SoC FPGA. The FIL test was performed to examine the PFC control with a hardware solution. In the FPGA in the loop (FIL) approach, the control algorithm is running in real time as the hardware. In the other hand, the controlled system and its components are simulated in Matlab environment. This technique combines between the software flexibility with real-time accuracy and hardware speed execution, in this paper, an FPGA in the loop control for the single-phase boost power factor corrector conditioner was performed to examine the PFC control with a Hardware solution. The main purpose of this research is the investigation of the hardware solution control technic applied on PFC converter.
A wide variety of maximum power point tracking (MPPT) algorithms for photovoltaic systems (PVS) have been proposed and developed. These MPPT algorithms vary in many aspects such as the selected criteria and techniques...
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ISBN:
(纸本)9781479982004
A wide variety of maximum power point tracking (MPPT) algorithms for photovoltaic systems (PVS) have been proposed and developed. These MPPT algorithms vary in many aspects such as the selected criteria and techniques used. In this paper, we propose an effective design methodology for hardware implementation of PVS into FPGA/ASICs. To achieve our goal, we propose the application of the model based design at high level using the Matlab/Simulink which includes the hdl coder Tool. The approach will assist the designer to develop and prototype in a relatively short time by eliminating time consuming and error prone due to manual coding. The proposed design methodology has been applied to the well know Pertub and Observe (P&O) MPPT controller. The Matlab/Simulink model of the P&O controller is optimized and converted to target, Hardware Description Language (hdl) code for FPGA/ASIC. The whole architecture of the P&O controller has been implemented on a Xilinx Spartan3E prototyping board. We demonstrate that the generated RTL code can be easily mapped into FPGA/ASICs, which allow the rapid prototyping of PVS with more complex algorithms.
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