检索结果-内蒙古大学图书馆

5th International Conference on the Development of Biomedical Engineering in Vietnam

作者： Othman, Norliza Jabbar, Mohamad Hairol Mahamad, Abd Kadir Mahmud, Farhanahani Univ Tun Hussein Onn Malaysia UTHM Cardiol & Physiome Anal Res Lab Batu Pahat Johor Malaysia Univ Tun Hussein Onn Malaysia UTHM Manycore Syst Chip MCSoC Res Lab Microelect & Nanotechnol Shamsudin Res Ctr MiNT S Batu Pahat Johor Malaysia Univ Tun Hussein Onn Malaysia UTHM Fac Elect & Elect Engn Batu Pahat Johor Malaysia

ISBN: (纸本)9783319117768;9783319117751

Cardiac excitation is a fundamental mechanism within the heart's function. One way to understand this mechanism is by using numerical modeling techniques. However, an immense amount of computational time has been required in the simulation that generally involves a large number of parameters. In this paper a simulation study of Luo Rudy Phase I (LR-I) mathematical model by using MATLAB Simulink to solve ordinary differential equations (ODEs) using field programmable gate array (FPGA) towards a real-time simulation of cardiac excitation has been presented. The FPGA could be the best solutions because it is able to provide high performance in solving higher order ODEs for real-time hardware implementation. In fact, the FPGA hardware design can be accelerated by using MATLAB Simulink hdl coder that automates the hardware description language (hdl) code generation from designed MATLAB Simulink blocks. Furthermore, hdl designed implementation can be verified by using hdl Verifier such as co-simulation and FPGA-in-the-Loop (FIL) approaches to simulate the generated hdl code and verify the results. In this paper, results show that the LR-I cardiac excitation modeling is successfully simulated by the MATLAB Simulink and by using the hdl coder the designed MATLAB Simulink model is successfully converted into Vhdl code and verified through the FIL. These have given a positive outlook towards the FPGA hardware implementation for real-time simulation.

关键词： Ordinary Differential Equations Luo-Rudy Phase I model Field Programmable Gate Array FPGA-in-the-loop simulation cardiac hdl coder

来源：评论

学校读者我要写书评

暂无评论

A Rapid Development Technique for Prototype FPGA Controllers

A Rapid Development Technique for Prototype FPGA Controllers

引用

International Conference on Inventive Systems and Control (ICISC)

作者： Sumam, M. J. Shiny, G. Coll Engn Trivandrum Dept Elect & Commun Power Elect Res Lab Thiruvananthapuram Kerala India

ISBN: (纸本)9781509047154

Advancements in solid state devices, programmable logic devices and Electronic Design Automation (EDA) tools have given a tremendous support to the development of digital controllers. High performance motor controllers usually require complex algorithm and long computation time. This makes the implementation task more complex. Features of parallel processing and high speed computing of Field Programmable Gate Array (FPGA) can be made use to face these challenges. This paper brings out the design procedure of a prototype Space Vector Pulse Width Modulated (SVPWM) FPGA controller. The scheme can be extended to multilevel SVPWM inverters, which require complex algorithm and long computation time. The algorithm is first implemented in SIMULINK models from hdl coder Library. hdl coder then converts it to optimized and synthesizable Very High Speed Integrated Circuit Hardware Description Language (Vhdl) code. The generated code is verified using hdl co-simulation model to make it error free. The code executed on FPGA with the help of a synthesis tool. This prototype FPGA digital controller is experimentally tested on the inverter that drives a 2-HP, 3-phase induction motor. The proposed method help researchers to create, simulate, verify and develop complex systems within short span of time with high degree of accuracy and reliability.

关键词： FPGA hdl coder Workflow advisor SVPWM

来源：评论

学校读者我要写书评

暂无评论

Leveraging Mathworks Tools to Accelerate the Prototyping of Custom 5G Applications in Hardware

Leveraging Mathworks Tools to Accelerate the Prototyping of ...

引用

IEEE High Performance Extreme Computing Virtual Conference (HPEC)

作者： Geyster, Joshua Gettings, Karen Monticciolo, Paul Rebholz, Matthew MIT Lincoln Lab Open & Embedded Syst Lexington MA 02421 USA MIT Lincoln Lab Adv RF Tech & Syst Lexington MA USA

ISBN: (纸本)9798350308600

The ubiquity and flexibility of 5G networks make it an attractive technology to customize for particular needs. In this work, we highlight some of the challenges associated with implementing custom 5G applications in hardware and the growing trend of utilizing high-level synthesis tools to relieve these issues. We present an overview of the 5G resource grid and the MATLAB-Simulink-hdl coder workflow. We then demonstrate the workflow through an example 5G resource grid transmitter design.

关键词： 5G Custom 5G MATLAB Simulink hdl coder HLS Hardware Implementation 5G Transmitter

来源：评论

学校读者我要写书评

暂无评论

FPGA Implementation for Cardiac Excitation-Conduction Simulation Based on FitzHugh-Nagumo Model 5

FPGA Implementation for Cardiac Excitation-Conduction Simula...

引用

5th International Conference on the Development of Biomedical Engineering in Vietnam

作者： Adon, Nur Atiqah Jabbar, Mohamad Hairol Mahmud, Farhanahani Univ Tun Hussein Onn Malaysia UTHM Fac Elect & Elect Engn Microelect & Nanotechnol Shamsudin Res Ctr MiNT S Cardiol & Physiome Anal Res Lab Batu Pahat Johor Malaysia Univ Tun Hussein Onn Malaysia UTHM Fac Elect & Elect Engn Microelect & Nanotechnol Shamsudin Res Ctr MiNT S Manycore Syst Chip MCSoC Res Lab Batu Pahat Johor Malaysia

ISBN: (纸本)9783319117768;9783319117751

The paper examines a method for development of a Field Programmable Gate Array (FPGAs)-based implementation of hardware model for the electrical excitation-conduction in cardiac tissue based on FitzHugh-Nagumo (FHN) mathematical model towards real-time simulation. The FHN model is described by a set of nonlinear Ordinary Differential Equations (ODEs) that includes two dynamic state variables for describing the excitation and the recovery states of a cardiac cell and the model is able to reproduce many characteristics of electrical excitation in cardiac tissues. In this paper, one dimensional (1D) FHN cable model is designed using MATLAB Simulink in order to simulate the conduction of cardiac excitation in coupled nonlinear systems of the heart dynamics. The designed MATLAB Simulink model is then being used for Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (Vhdl) code generation by using hdl coder that will be implemented on a hardware design FPGA platform of Xilinx Virtex-6 FPGA board. In order to verify and analyze the designed algorithm on the platform, hdl Verifier is used through co-simulation with FPGA-in-the-loop (FIL) simulation and it has shown a significant result which has increased confidence that the algorithm will work in the real FPGA stand-alone application. Therefore, these approaches provide an effective FPGA design flow towards a stand-alone implementation to perform real-time simulations of the cellular excitation-conduction in a large scale cell models.

关键词： Field Programmable Gate Array FitzHugh-Nagumo excitation-conduction FPGA-in-the-loop simulation hdl coder

来源：评论

学校读者我要写书评

暂无评论

Design and Implementation of a Low-Cost FPGA Based Real-Time Simulator for a Three-Phase Grid Emulator Including Neutral

Design and Implementation of a Low-Cost FPGA Based Real-Time...

引用

2023 IEEE International Conference on Electrical, Computer and Energy Technologies, ICECET 2023

作者： Nzimbakani, Katria Kamiantako Lusala, Angelo Kuti Ndeko, J.M. Moanda Gyselinck, Johan Faculté Polytechnique Université de Kinshasa Kinshasa Democratic Republic Congo Beams Department Université Libre de Bruxelles Brussels Belgium

ISBN: (纸本)9798350327816

This paper presents the design and the implementation of a low-cost FPGA-based real-time simulator for a grid emulation system including neutral. The real-time simulator for the proposed grid emulator is implemented in an open-loop version. No feedback mechanism or specific controllers are needed. That makes the design simple, low-cost, fast, and easy to implement while reducing the risk of system instability. The design process combines high-level Simulink models with hdl code generation and FPGA synthesis implementation in order to control the grid emulator. The control of the three-phase four-leg grid emulator is implemented using a PWM method based on a triangular carrier wave involving the concept of offset voltage to reach better PWM performances while reducing FPGA resource utilization. Experimental results carried out show the effectiveness of the proposed design that can track the reference with high precision, less than 1.6% of relative error compared to the reference, while achieving fast transient performance. © 2023 IEEE.

关键词： digital control Field Programmable Gate Array (FPGA) fixed-point representation four-leg inverter grid disturbances Grid emulator hdl coder Power Hardware-in-the-Loop (PHIL) Pulse Width Modulation (PWM) Vhdl

来源：评论

学校读者我要写书评

暂无评论

Data Set Development for Gesture Recognition and Implementation using MATLAB and Xilinx Vivado

Data Set Development for Gesture Recognition and Implementat...

引用

2023 International Conference on Evolutionary Algorithms and Soft Computing Techniques, EASCT 2023

作者： Madhavan, Sowmya Hegde, Ashwini N Nitte Meenakshi Institute of Technology Dept. of Electronics and Communication Engineering Bangalore India

ISBN: (纸本)9798350313413

Gesture recognition system is an algorithmic based system which can interpret different hand gestures, which are useful in human machine interface. In this paper, two datasets are used for training and testing. The first data set developed by the authors, has a total of 250 images, across 10 classes. Images of ten different hand gestures of one of the authors were captured and segregated into ten corresponding classes. For each hand gesture, 25 different images are captured in varying positions. To increase number of images in the data set, a second data set which consists of 1000 images, across 10 classes, is also considered from an open source. In the first data set, 250 images are considered for training and the resolution of each image is 432 x 578. In the second data set, 1000 images are used for training. The trained images are converted into gray scale and stored in the binary format. A gesture recognition algorithm is designed and 90 images are used for testing in both datasets. The gesture recognition algorithm is modeled in MATLAB for accuracy of 99.2% for the first data set and 98.6% for the second data set. The next stage of the project is conversion of designed MATLAB code into verilog code using hdl coder. The verilog code is functionally simulated, synthesized, and implemented in Xilinx vivado. © 2023 IEEE.

关键词： Gesture recognition hdl coder Implementation MATLAB Synthesis Testing Training Xilinx Vivado

来源：评论

学校读者我要写书评

暂无评论

A method for Rapid Deployment of Brushless DC Motor Servo System Model Based on FPGA

A method for Rapid Deployment of Brushless DC Motor Servo Sy...

引用

作者： Wang Bolun Zhang Tao Shi Zhengjin Zhang Hualiang Xie Feng Liu Zihong School of Automation and Electrical Engineering Shenyang Ligong University Shenyang Institute of Automation Chinese Academy of Sciences Key Laboratory of Networked Control Systems Chinese Academy of Sciences Institutes for Robotics and Intelligent Manufacturing Chinese Academy of Sciences School of Electrical Engineering Dalian University of Technology

Recently,with the development of technology and the lucubrate of automation technology,the dependence of modern industry on synchronous motors has gone deep into the *** fact,the current complex control algorithms consume the computing power of the data processing chips and put forward a higher request to the ability of ***,the emphasis of this study lies in a rapid deployment method of a brushless DC motor servo control system based on the model *** using Simulink software to simulate and verify the three-closed-loop servo model of the DC brushless motor,Verilog or Vhdl language code will be generated,which can automatically configure the project according to the ***,a drive and control hardware platform based on Xilinx Zynq-7000 chips was built to verify the feasibility,the experimental results indicate that the proposed method can effectively simplify the deployment of complex algorithm codes,reduce the development cycle of brushless DC motor servo system with strong engineering practicability.

关键词： MBD hdl coder BLDC Servo Control

来源：评论

学校读者我要写书评

暂无评论

Multi-Bit Digital Receiver Design For Radar Signature Estimation

Multi-Bit Digital Receiver Design For Radar Signature Estima...

引用

IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology

作者： Deeksha Gupta A. A. Bazil Raj Abhijit Kulkarni Dept. of Electronics Engineering Defence Institute of Advanced Technology Defence Avionic Research Establishment DARE

ISBN: (数字)9781538624401

ISBN: (纸本)9781538624418

This paper brings out a unique FPGA based pulse detection and characterization approach for digital wideband ESM receiver targeted for EW applications. The proposed approach uses a high speed ADC and FPGA based architecture for sampling and digital signal processing of the received RADAR signals to extract the key parameters such as Frequency (F), Time of Arrival (TOA), Pulse Width (PW) and Pulse Repetition Interval (PRI). The proposed novel FFT based digital EW receiver is designed and verified by MATLAB and SIMULINK tools and Vhdl code for same algorithm is generated using hdl coder for FPGA implementation. The current paper uses 512-point FFT based digital EW receiver, requires minimum pulse width of 750 ns and frequency separation between two simultaneous pulses is 2.63 MHz to extract the key parameters accurately. The simulated and measured results for Pulse detection algorithm are presented.

关键词： EW ESM Digital receiver LPI POI ADC FFT Peak detection Intermediate frequency (IF) hdl coder FPGA Vhdl Pulse description words (PDW) Digital receiver Field programmable gate arrays electronic warfare peak detection very high density lipoproteins Fast Fourier transform LPI LYSINURIC PROTEIN INTOLERANCE POIs European Stability Mechanism PULSE WIDTH analog digital converter

来源：评论

学校读者我要写书评

暂无评论

Fixed-point Simulink Designs for Automatic hdl Generation of Binary Dilation ＆ Erosion

Fixed-point Simulink Designs for Automatic HDL Generation of...

引用

International Conference on Computer Science and Information Systems (ICSIS’2014, Dubai)

作者： Gurpreet Kaur Nancy Gupta Mandeep Singh Department of ECE CT Institute of EngineeringManagement and Technology

Embedded Imaging is a technique used to develop image processing based standalone hardware systems and involves the on-board implementations of image based operations on platforms like *** implementations require low-level description of desired operation using Vhdl/Verilog.A digital image is a 2-dimensional array of discrete pixel *** involves lot of complexity for describing a pixel level image based operation in *** like hdl-coder in MATLAB may reduce this complexity by automatically generating a synthesizable hdl code from Simulink Models that are designed using fixed-point *** paper proposes the design of fixed-point coding scheme of Morphological Image Processing operations:Binary dilation ＆ erosion for automatic generation of hdl *** is concluded that the output images generated through proposed fixed point Simulink models are not only qualitatively better but the generated Vhdl codes also resulted in successful synthesization on Spartan6 FPGA.

关键词： Embedded Imaging Fixed-point arithmetic FPGA hdl coder Morphological Image Procesing Simulink

来源：评论

学校读者我要写书评

暂无评论

Fast FPGA Prototyping based Real-Time Image and Video Processing with High-Level Synthesis

引用

INTERNATIONAL JOURNAL OF ADVANCED COMPUTER SCIENCE AND APPLICATIONS 2020年第2期11卷 108-116页

作者： Ghodhbani, Refka Horrigue, Layla Saidani, Taoufik Atri, Mohamed Univ Monastir Lab Elect & Microelect Fac Sci Monastir Monastir Tunisia Northern Border Univ Rafha Dept Comp Sci Fac Comp & Informat Technol Rafha Saudi Arabia King Khalid Univ Coll Comp Sci Abha Saudi Arabia

Programming in high abstraction level is known by its benefits. It can facilitate the development of digital image and video processing systems. Recently, high-level synthesis (HLS) has played a significant role in developing this field of study. Real time image and video Processing solution needing high throughput rate are often performed in a dedicated hardware such as FPGA. Previous studies relied on traditional design processes called Vhdl and Verilog and to synthesize and validate the hardware. These processes are technically complex and time consuming. This paper introduces an alternative novel approach. It uses a Model-Based Design workflow based on hdl coder (MBD), Vision hdl Toolbox, Simulink and MATLAB for the purpose of accelerating the design of image and video solution. The main purpose of the present paper is to study the complexity of the design development and minimize development time (Time to market: TM) of conventional FPGA design. In this paper, the complexity of the development (TM) can be reduced by 60% effectively by automatically generating the IP cores and downloading the modeled design through the Xilinx tools and give more advantages of FPGA related to the other devices like ASIC and GPU.

关键词： High-level synthesis FPGA fast prototyping real-time image processing video surveillance computer-aided design model-based design hdl coder FPGA

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：