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Parallel In-Loop Filtering in hevc encoder on GPU

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2018年第3期64卷 276-284页

作者： Wang, Yang Guo, Xun Fan, Xiaopeng Lu, Yan Zhao, Debin Gao, Wen Harbin Inst Technol Dept Comp Sci & Technol Harbin 150001 Heilongjiang Peoples R China Microsoft Res Asia Beijing 100080 Peoples R China Peking Univ Dept Elect Engn & Comp Sci Beijing 100871 Peoples R China

In-loop filtering is an important part of high efficiency video coding (hevc), which consists of deblocking filter and sample adaptive offset (SAO) filter. It can not only improve the compression efficiency of hevc, but also improve the visual quality of the reconstructed videos significantly. However, the high computational complexity hampers its applications for real-time encoding scenarios. In this paper, we propose a parallel strategy for in-loop filtering in hevc encoder on graphics processing unit (GPU). In the proposed strategy, the pipeline structure for hevc encoding by parallel processing deblocking filter and SAO on GPU is described first. Then, the joint optimization for deblocking filter and SAO on GPU is detailed by parallel processing of deblocking filter and parallel processing of SAO separately. The joint optimization can improve the degree of parallelism and ease the computational burden of the CPU. Experimental results demonstrate that the proposed method can achieve about 47% (up to 67%) time saving on average for test sequences.

关键词： hevc encoder in-loop filter GPU deblocking filter SAO

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Implementation of fast hevc encoder based on SIMD and data-level parallelism

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EURASIP JOURNAL ON IMAGE AND VIDEO PROCESSING 2014年第1期2014卷 1-19页

作者： Ahn, Yong-Jo Hwang, Tae-Jin Sim, Dong-Gyu Han, Woo-Jin Kwangwoon Univ Dept Comp Engn Seoul 4471 South Korea Gachon Univ Dept Software Design & Management Songnam 461701 Gyeonggi South Korea

This paper presents several optimization algorithms for a High Efficiency Video Coding (hevc) encoder based on single instruction multiple data (SIMD) operations and data-level parallelism. Based on the analysis of the computational complexity of hevc encoder, we found that interpolation filter, cost function, and transform take around 68% of the total computation, on average. In this paper, several software optimization techniques, including frame-level interpolation filter and SIMD implementation for those computationally intensive parts, are presented for a fast hevc encoder. In addition, we propose a slice-level parallelization and its load-balancing algorithm on multi-core platforms from the estimated computational load of each slice during the encoding process. The encoding speed of the proposed parallelized hevc encoder is accelerated by approximately ten times compared to the hevc reference model (HM) software, with minimal loss of coding efficiency.

关键词： hevc hevc encoder SIMD implementation Slice-level parallelism Load balancing

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Investigation of filtering of rain streaks affected video sequences under various quantisation parameter in hevc encoder using an enhanced V-BM4D algorithm

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IET IMAGE PROCESSING 2020年第2期14卷 337-347页

作者： Jayaraman, Thiyagarajan Chinnusamy, Gowri Shankar KSR Coll Engn Dept Elect & Elect Engn Namakkal Tamil Nadu India

This study proposes an enhanced video block matching four-dimensional (V-BM4D) denoising algorithm for highly correlated rain streaks pattern video sequence in high-efficiency video coding (hevc) encoder. Removal of structural rain streaks from high definition (HD) video sequences are challenging issues in real-time video application. Temporal information of original video sequences is distorted among the successive video frames due to the presence of natural degradation parameters such as fog, smog and rain streaks. Rain streaks are highly correlated structural noise pattern, which affects the nature of video frame compared to other natural degradations. Existing hevc encoder is employed with in-loop filtering to protect the temporal information of original video sequences from rain streaks pattern. However, in-loop filtering is unable to remove the highly directional oriented rain pattern from video frames. To retain temporal information among the successive video frames, enhanced block matching denoising block is adopted in hevc coder. The proposed enhanced VBM4D- based in-loop filtering eliminates the various level of rain streaks from the HD video sequences by temporal information prediction in 4D platform. Experimental results demonstrate that the proposed denoising algorithm yields better peak signal to noise ratio value and provides better bit rate saving for various hevc configuration.

关键词： image matching video coding image denoising image sequences image filtering image enhancement hevc encoder enhanced V-BM4D algorithm high-efficiency video coding encoder high definition video sequences real-time video application temporal information natural degradation parameters structural noise pattern enhanced block matching denoising block enhanced V-BM4D-based in-loop filtering HD video sequences highly directional oriented rain streak pattern video block enhancement high definition video sequences quantisation parameter hevc reference software HM16 0 peak signal to noise ratio value

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hevc encoder for Super Hi-Vision

HEVC Encoder for Super Hi-Vision

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IEEE International Conference on Consumer Electronics (ICCE)

作者： Iguchi, Kazuhisa Ichigaya, Atsuro Sugito, Yasuko Sakaida, Shinichi Shishikui, Yoshiaki Hiwasa, Norimichi Sakate, Hiroharu Motoyama, Nobuaki NHK Japan Broadcasting Corp Tokyo Japan Mitsubishi Electr Corp Kamakura Kanagawa Japan

ISBN: (纸本)9781479912919

This paper describes the world's first hevc (High Efficiency Video Coding) hardware encoder for SHV (Super Hi-Vision). SHV is an 8K UHDTV (Ultra-High Definition Television) system that has a 7,680 x 4,320 pixel resolution. The developed encoder compresses SHV pictures in real-time using 17 encoding units. The coded picture provides acceptable level of image quality without major defect at 85 Mbps.

关键词： high definition television video codecs video coding 8K UHDTV system hevc encoder SHV pictures Super Hi-Vision bit rate 85 Mbit/s high efficiency video coding hardware encoder image quality ultra-high definition television system Bit rate Broadcasting Codecs Encoding HDTV Hardware Video coding

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Profiling of hevc encoder

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ELECTRONICS LETTERS 2014年第15期50卷 1062-U40页

作者： Saab, F. Elhajj, I. H. Kayssi, A. Chehab, A. Amer Univ Beirut Elect & Comp Engn Dept Beirut Lebanon

One of the serious challenges facing smartphones and other portable devices nowadays is battery life. A typical smartphone user will be running several applications on the device at any given time, and most of these applications consume plenty of energy. In fact, some of the most energy-consuming applications are those related to video conferencing and streaming. There is a lot of work to improve the energy efficiency of such applications by improving the energy efficiency of the underlying encoders. However, to accomplish that, full profiling of the encoder must be performed first. The results of profiling the High Efficiency Video Coding (hevc) are presented. Results are presented in terms of types of assembly level instructions in every function of the encoder. Thus, depending on the environment on which the encoder is running, the energy consumed for any type of instruction can be obtained. The results show that, in an hevc encoding process, about 48% of the instructions are memory related and about 18-20% are arithmetic operations. This result is very important for any work in energy analysis and optimisation of the hevc encoder.

关键词： battery life Electrical/electronic equipment (energy utilisation) energy-consuming applications energy analysis Mobile radio systems high efficiency video codec smartphones hevc encoding process optimisation hevc encoder smart phones video conferencing telecommunication power management video streaming energy optimisation Image and video coding Optimisation techniques portable devices energy efficiency video coding

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Adaptive block searching and fractional rate-distortion trade-off based motion estimation for hevc encoder

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EVOLUTIONARY INTELLIGENCE 2022年第2期15卷 1395-1409页

作者： Jankar, Jayashree R. Shah, Sanjeevani K. Maharashtra Inst Technol MIT Pune Maharashtra India Smt Kashibai Navale Coll Engn SKN COE Post Grad Dept E&TC Pune Maharashtra India

In H.265/high efficiency video coding encoding, the cost function is a significant feature that decides the mode and structure of the encoding and the effectiveness of the methods relies on the coding efficiency, minimal rate-distortion optimization, and encoding time. The issues associated with the aforementioned factors are tackled effectively by proposing a new block search, an Adaptive block searching algorithm (AdBS) along with the fractional rate-distortion trade-off (fractional RD trade-off). The motion estimation using the proposed Adaptive block searching algorithm uses the heptagon block search patterns with eight checkpoints in such a way to assure the fast processing, contributing towards the minimal encoding process. The coding efficiency is enhanced twice with the assured reconstruction quality and bandwidth. The analysis is performed with single and multiple videos obtained from the CIPR SIF Sequences database and the analysis in terms of Structural Similarity Index (SSIM), Peak signal-to-noise ratio (PSNR), and average time reveals the effectiveness of the proposed AdBS and fractional RD-trade-off- based motion estimation. The PSNR, SSIM, and average time of the proposed method are found to be 85.6548%, 45 dB, and 565 nano-secs for single videos and 88.9841%, 45 dB, and 2584 nano-secs for the multiple videos.

关键词： Rate-distortion Block search Motion estimation hevc encoder Fractional calculus

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Hardware Deceleration of Kvazaar hevc encoder 19th

Hardware Deceleration of Kvazaar HEVC Encoder

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19th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

作者： Sainio, Joose Mercat, Alexandre Vanne, Jarno Tampere Univ Tampere Finland

ISBN: (纸本)9783030275624;9783030275617

High Efficiency Video Coding (hevc) doubles the coding efficiency of the prior Advanced Video Coding (AVC) standard but tackling its huge complexity calls for efficient hevc codec implementations. The recent advances in Graphics Processing Units (GPUs) have made programmable general-purpose GPUs (GPGPUs) a popular option for accelerating various video coding tools. Massively parallel GPU architectures are particularly well suited for hardware-oriented full search (FS) algorithm in hevc integer motion estimation (IME). This paper analyzes the feasibility of a GPU-accelerated FS implementation in the practical Kvazaar open-source hevc encoder. According to our evaluations, implementing FS on AMD Radeon RX 480 GPU makes Kvazaar 12.5 times as fast as the respective anchor implemented entirely on an Intel 8-core i7 processor. However, the obtained speed gain is lost when fast IME algorithms are put into use in the anchor. For example, executing the anchor with hexagon-based search (HEXBS) algorithm is almost two times as fast as our GPU-accelerated proposal and the benefit of GPU offloading is reduced to a slight coding gain of 1.2%. Our results show that accelerating IME on a GPU speeds up non-practical encoders due to their enormous inherent complexity but the price paid with practical encoders tends to be too high. Conditional processing schemes of fast IME algorithms can be efficiently executed on processors without any substantial coding loss over that of FS. Nevertheless, we still believe there might be room for exploiting GPU on IME acceleration but GPU-parallelized fast algorithms are needed to get value for additional implementation cost and power budget.

关键词： High Efficiency Video Coding (hevc) hevc encoder Graphics Processing Unit (GPU) Integer Motion Estimation (IME) Full-Search (FS)

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hevc Video encoder implementation On Texas Instruments Platforms 17

HEVC Video encoder implementation On Texas Instruments Platf...

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17th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA)

作者： Bahri, Nejmeddine el Ansari, Abdessamad Maazouz, Mohamed Ahaitouf, Ali Masmoudi, Nouri Univ Sfax LETI Lab Natl Sch Engineers Sfax Tunisia Sidi Mohammed Ben Abdellah Univ RESS Lab Fes Morocco Univ Medea LSEA Lab Medea Algeria

ISBN: (纸本)9781509034079

this paper presents a high efficiency video encoder implementation (hevc) on two different Texas Instruments (TI) platforms: the BeagleBoard-xM based on ARM processor and the TMS320C6678 DSP. The new features of these processors such as multicore architecture, high frequency processor and low power consumption motivate researchers to develop an embedded hevc video encoder which could be exploited in several multimedia applications such as High Definition (HD)TV, smart cameras, HD video conference, Ultra HD video surveillance systems. Different operating systems (OS) with different compilers are tested in order to obtain an optimized hevc encoder implementation. Experimental results show that hevc encoder DSP-based solution using SYS BIOS real time OS allows saving up to 62% of encoding time compared to Linux-c6x OS with the same DSP and about 71% of encoding time compared to BeagleBoard-based solution without inducing any performance degradation in terms of video quality or bitrate.

关键词： hevc encoder DSP ARM processor RTOS Cross-Compilation

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A Fast hevc Encoding Method Using Depth Information of Collocated CUs and RD Cost Characteristics of PU Modes

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IEEE TRANSACTIONS ON BROADCASTING 2017年第4期63卷 680-692页

作者： Tai, Kuang-Han Hsieh, Min-Yuan Chen, Mei-Juan Chen, Chia-Yen Yeh, Chia-Hung Natl Dong Hwa Univ Dept Elect Engn Hualien 97401 Taiwan Univ Auckland Dept Comp Sci Auckland 1142 New Zealand Natl Taiwan Normal Univ Dept Elect Engn Taipei 10610 Taiwan Natl Sun Yat Sen Univ Dept Elect Engn Kaohsiung 80424 Taiwan

The latest video coding standard, high efficiency video coding (hevc), aims to achieve better coding efficiency than the H. 264/AVC standard. To improve the coding performance of hevc, tools and structures are included that also increase the computational complexity of encoding, especially for the mode decisions in the coding unit (CU), which is a structural element in the hevc. For each CU size, the hevc encoder performs mode decision and motion estimation using all prediction unit (PU) types and incurs massive computational burdens. In this paper, we investigate the depth correlation between the current and the collocated CU to avoid irrelevant CU procedure and truncate some PU predictions as a result. We also investigate the relationship of the rate-distortion (RD) costs after the Merge/SKIP prediction. By analyzing different CU sizes and quantization parameters, we build a mathematical model to represent the relationship for the RD costs after the Merge/SKIP prediction with an adaptive termination of the CU procedure. In addition, the relationship of the RD costs after the Merge/SKIP prediction and 2N x 2N mode is also explored. Search range reduction is used to further speed up our algorithm. Experimental results show that our algorithm can reduce the coding time by up to 80%, and provide average coding time savings of 46%, 45%, and 52%, for low delay B, low delay P, and random access configurations, respectively. Moreover, the proposed algorithm is able to maintain coding performance similar to HM 11.0. The proposed scheme outperforms previous work in terms of both the coding speed and the RD performance.

关键词： hevc encoder coding unit prediction unit rate-distortion cost early termination mode decision

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Fast algorithm for hevc intra-coding implemented by preprocessing

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IET IMAGE PROCESSING 2019年第9期13卷 1578-1586页

作者： Mu, Weijia Liang, Yu Xu, Shiwei Zhang, Wei Liu, Yanyan Tianjin Univ Sch Elect Informat Engn Tianjin 300072 Peoples R China Sci & Technol Electroopt Informat Secur Control L Tianjin 300308 Peoples R China Nankai Univ Coll Elect Informat & Opt Engn Tianjin 300071 Peoples R China

Compared to previous video compression standards H.264/AVC, high-efficiency video coding (hevc) introduces a recursive quad-tree structure in intra-coding and adds intra-mode from 9 to 35 to achieve higher coding efficiency. The update significantly improves the performance of intra-coding. However, it greatly increases the amount of computation, and this will increase the need for the fast algorithm and hardware design that can satisfy the real-time encoding of hevc encoder. In this study, the authors propose a fast intra-coding algorithm based on analysis of original pixel gradient texture. The algorithm consists of two steps, fast coding unit size decision and reduction of candidate modes. The experimental results show that compared with the HM16.7 encoder, the optimisation algorithm can obtain 50.7% time reduction on average with 1.32% Bjontegaard distortion (BD)-rate increase and 0.07 dB BD-peak-signal-to-noise ratio loss. Meanwhile, this study designs a pre-processing hardware structure based on original pixels. With TSMC 90 nm complementary metal oxide semiconductor technology, the proposed structure can achieve 625 MHz working frequency at the cost of 2094 gates, which can fulfil the throughput requirement of 8K x 4K@46 fps real-time encoding.

关键词： video coding data compression optimisation CMOS integrated circuits quadtrees hevc intra-coding high-efficiency video coding recursive quad-tree structure real-time encoding hevc encoder optimisation algorithm pre-processing hardware structure video compression standards H 264-AVC pixel gradient texture Bjontegaard distortion size 90 0 nm frequency 625 0 MHz TSMC complementary metal oxide semiconductor technology

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