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A multi-processing architecture for accelerating haar-based face detection on FPGA 9

A multi-processing architecture for accelerating Haar-based ...

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9th Int Conf Ind Information Syst (ICIIS2014)

作者： Kumar, Chanchal Azam, Md Shadab Indian Inst Technol Dept Elect & Commun Engn Roorkee Uttarakhand India

ISBN: (纸本)9781479964994

Obtaining a real-time implementation for a face detection system is the first step towards human-machine interaction. This paper presents an architecture, implementable on an FPGA, for accelerating the haar-based face detection algorithm through use of multiple dedicated processing units by utilizing the inherent parallelism in the algorithm. The architecture is designed to be scalable and the face detection load has been distributed among the processing units so as to reduce the idle time. The design has been synthesized for the Xilinx Virtex-5 board. Use of a single processing unit gives an improvement in the face detection frame rate of 5.45 times over an Intel i5, 2.4 GHz processor. The frame rate is further doubled by scaling the architecture to include four processing units running in parallel.

关键词： face recognition feature extraction field programmable gate arrays human computer interaction FPGA haar-based face detection algorithm Xilinx Virtex-5 board face detection frame rate improvement face detection load distribution face detection system human-machine interaction idle time reduction multiprocessing architecture parallelism processing units real-time implementation scalable architecture design Acceleration Computer architecture face face detection Feature extraction Field programmable gate arrays Parallel processing Field programmable gate arrays Facial Recognition Feature extraction acceleration computer human interaction Computer Architecture detection systems parallelism PARALLEL PROCESSING (COMPUTERS) Human machine interaction face face

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A novel architecture for dynamic Integral Image generation for haar-based face detection on FPGA

A novel architecture for dynamic Integral Image generation f...

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IEEE Region 10 Conference (TENCON)

作者： Kumar, Chanchal Agarwal, Sankalp Indian Inst Technol Dept Elect & Commun Engn Roorkee Uttarakhand India

ISBN: (纸本)9781479940752

Integral Image generation is an important step in the haar-based face detection algorithm and plays a vital role in the optimization of the algorithm for real-time implementation by evaluating each of the thousands of haar-features in constant time. The integral image of a frame needs to be generated as a pre-processing stage before running the haar-classifier on the detection windows within the frame. The delay required in the pre-processing stage is directly proportional to the resolution of the frame and becomes substantial with increasing resolution, limiting the real-time operation of the entire algorithm. This paper presents a novel architecture for generating the integral images of the current detection window dynamically, such that the pre-processing delay is reduced substantially. It is shown that an improvement of 13.71 times is obtained for VGA frames by this approach. The usage of hardware resources is also reduced by around 50% compared to previous implementations.

关键词： haar transforms face recognition feature extraction field programmable gate arrays image classification image resolution integral equations FPGA haar-based face detection algorithm haar-classifier haar-features VGA frames detection windows dynamic integral image generation architecture field programmable gate array frame resolution hardware resources usage image preprocessing delay image preprocessing stage optimization Clocks Delays face Feature extraction Generators Image generation Image resolution Field programmable gate arrays Image generation image resolution Facial Recognition Feature extraction haar transforms Timing devices Image classification Integral equations dynamos face face delay

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