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APPROACH OF INTEGRATING BEHAVIOUR-DRIVEN DEVELOPMENT WITH hardware/software codesign

INTERNATIONAL JOURNAL OF INNOVATIVE COMPUTING INFORMATION AND CONTROL 2019年第3期15卷 1177-1191页

作者： Alhaj, Mohammad Arbez, Gilbert Peyton, Liam Al Ahliyya Amman Univ Fac Engn Amman 19328 Jordan Univ Ottawa Sch Elect Engn & Comp Sci 800 King Edward Ave Ottawa ON K1N 6N5 Canada

Using typical approaches in designing embedded systems to manage the specification and design of the hardware and software is not suitable in today's projects. In this paper, we propose a model-driven approach to integrate hardware/software codesign with Behaviour-Driven Development. hardware/software codesign approach allows the hardware and the software to be designed and implemented concurrently and optimizes the project design constraint, such as performance and cost. Behaviour-Driven Development spurs project stakeholders to collaborate to ensure the right software is developed to meet their needs and ensures that all project participants communicate in the same language. The approach exploits the advantages of each approach and provides the ability to describe the behaviour of the software as executable user stories in a hardware/software codesign environment. The approach is evaluated using a renewable energy project in collaboration with a private company in Canada to build a system for autonomous load management of self-forming renewable energy nanogrids.

关键词： Embedded systems Behaviour-Driven Development hardware/software codesign Test-driven development Nanogrid systems Agile software

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hardware/software codesign for Portable Optical Coherence Tomography (OCT) Applications 7

Hardware/Software Codesign for Portable Optical Coherence To...

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Joint 7th International Conference on Informatics, Electronics & Vision (ICIEV) / 2nd International Conference on Imaging, Vision and Pattern Recognition (icIVPR)

作者： Tang, Song-Nien Hsiang, Chih-Yu Huang, Sheng-Jie Chung Yuan Christian Univ Dept Informat & Comp Engn Taoyuan Taiwan

ISBN: (纸本)9781538651636

This paper presents a hardware-software codesign scheme for the image formation of the Fourier-domain optical coherence tomography (FDOCT) system. Using a hardware processor, the fast Fourier transform (FFT) together with its front-end DC noise removal and re-sampling operations can be efficiently performed. In cooperation with the hardware unit, a software platform can properly execute the flexible magnitude compression and dynamic range mapping which are associated with the OCT image display. Moreover, the calibration process can also be performed using the same software platform. The proposed design could be developed based on a small-scale system, which lends support to the trend of portable FDOCT applications. System-level design verification was performed using an FPGA module and a mobile phone to evaluate the efficacy of the proposed hardware/software codesign scheme. By accessing the raw data through a pattern generator, the 16.2-fps OCT image display (in the 1024x1000 resolution) can be achieved in the developed FPGA-phone verification system.

关键词： optical coherence tomography OCT Fourier-domai FDOCT hardware/software codesign

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hardware-software codesign of Wireless Transceivers on Zynq Heterogeneous Systems

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IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING 2018年第4期6卷 566-578页

作者： Drozdenko, Benjamin Zimmermann, Matthew Dao, Tuan Chowdhury, Kaushik Leeser, Miriam Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA

Recently, wireless technology has seen many new devices, protocols, and applications. As standards adapt to keep pace with hardware availability and user needs, the trend points towards systems that achieve high data rates with low energy consumption. Moreover, there is an emerging vision of a transceiver architecture that can adapt to multiple protocols, existing and evolving. This architecture maps computation to underlying heterogeneous computing elements, composed of processors and field programmable gate array (FPGA) fabric. Here, we introduce a method for modeling a generic orthogonal frequency division multiplexing (OFDM) wireless transceiver on the Zynq system-on-chip by decomposing the standard specifications into a set of functional blocks used in multiple protocols. Implementing the 802.11a physical (PHY) layer as an example, our approach creates Simulink model variants for both transmitter and receiver, each with a different boundary between hardware and software components. We use these models to generate hardware description language (HDL) code and bitstream for the programmable logic and C code with an executable for the advanced RISC machine (ARM) processor. We validate, profile, and analyze the models using metrics including frame time, resource utilization, and energy consumption. Our results demonstrate how to select a co-design configuration considering execution time and energy, and show how our platform can be reused for multiple-input multiple-output (MIMO) and protocol coexistence.

关键词： Heterogeneous (hybrid) systems reconfigurable hardware data communications devices receivers transmitters signal processing systems wireless communication wireless systems hardware/software interfaces hardware/software codesign

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An exercise on hardware/software codesign following the RISC model

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COMPUTER APPLICATIONS IN ENGINEERING EDUCATION 2016年第2期24卷 305-312页

作者： Joseph, Diya Kaur, Geetika Chakraborty, Pinaki Netaji Subhas Inst Technol Div Elect & Commun Engn New Delhi 110078 India Netaji Subhas Inst Technol Div Comp Engn New Delhi 110078 India

This paper presents an exercise to demonstrate the benefits of hardware/software codesign. A RISC processor and a high-level language have been designed together to make best use of the features of one another. A CPU simulator, an assembler and a compiler have been implemented based on the design. The exercise is suitable for students of computer engineering and electronics engineering students nearing their graduation. (c) 2015 Wiley Periodicals, Inc.

关键词： hardware/software codesign RISC CPU simulator assembler compiler

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A Computing-in-Memory-Based One-Class Hyperdimensional Computing Model for Outlier Detection

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IEEE TRANSACTIONS ON COMPUTERS 2024年第6期73卷 1559-1574页

作者： Wang, Ruixuan Moon, Sabrina Hassan Hu, Xiaobo Sharon Jiao, Xun Reis, Dayane Villanova Univ Dept Elect & Comp Engn Villanova PA 19085 USA Univ S Florida Dept Comp Sci & Engn Tampa FL 33620 USA Univ Notre Dame Dept Comp Sci & Engn Notre Dame IN 46556 USA

In this work, we present ODHD, an algorithm for outlier detection based on hyperdimensional computing (HDC), a non-classical learning paradigm. Along with the HDC-based algorithm, we propose IM-ODHD, a computing-in-memory (CiM) implementation based on hardware/software (HW/SW) codesign for improved latency and energy efficiency. The training and testing phases of ODHD may be performed with conventional CPU/GPU hardware or our IM-ODHD, SRAM-based CiM architecture using the proposed HW/SW codesign techniques. We evaluate the performance of ODHD on six datasets from different application domains using three metrics, namely accuracy, F1 score, and ROC-AUC, and compare it with multiple baseline methods such as OCSVM, isolation forest, and autoencoder. The experimental results indicate that ODHD outperforms all the baseline methods in terms of these three metrics on every dataset for both CPU/GPU and CiM implementations. Furthermore, we perform an extensive design space exploration to demonstrate the tradeoff between delay, energy efficiency, and performance of ODHD. We demonstrate that the HW/SW codesign implementation of the outlier detection on IM-ODHD is able to outperform the GPU-based implementation of ODHD by at least 331.5x889 x in terms of training/testing latency (and on average 14.0x36.9x in terms of training/testing energy consumption).

关键词： Anomaly detection Task analysis Training Testing software algorithms Forestry Computers Hyperdimensional computing outlier detection computing-in-memory hardware/software codesign

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software/hardware codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level Synthesis and Register-Transfer Level Design Methodologies 29

Software/Hardware Codesign of the Post Quantum Cryptography ...

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29th International Conference on Field-Programmable Logic and Applications (FPL)

作者： Farahmand, Farnoud Duc Tri Nguyen Dang, Viet B. Ferozpuri, Ahmed Gaj, Kris George Mason Univ Dept Elect & Comp Engn Fairfax VA 22030 USA

ISBN: (纸本)9781728148847

When quantum computers become scalable and reliable, they are likely to break all public-key cryptography standards, such as RSA and Elliptic Curve Cryptography. The projected threat of quantum computers has led the U.S. National Institute of Standards and Technology (NIST) to an effort aimed at replacing existing public-key cryptography standards with new quantum-resistant alternatives. In December 2017, 69 candidates were accepted by NIST to Round 1 of the NIST Post-Quantum Cryptography (PQC) standardization process. NTRUEncrypt is one of the most well-known PQC algorithms that has withstood cryptanalysis. The speed of NTRUEncrypt in software, especially on embedded software platforms, is limited by the long execution time of its primary operation, polynomial multiplication. In this paper, we investigate speeding up NTRUEncrypt using software/hardware codesign on a Xilinx Zynq UltraScale+ multiprocessor system-on-chip (MPSoC). Polynomial multiplication is implemented in the Programmable Logic (PL) of Zynq using two approaches: traditional Register-Transfer Level (RTL) and High-Level Synthesis (HLS). The remaining operations of NTRUEncrypt are executed in software on the Processing System (PS) of Zynq, using the bare-metal mode. The speed-up of our software/hardware codesigns vs. purely software implementations is determined experimentally and analyzed in the paper. The results are reported for the RTL-based and HLS-based hardware accelerators, and compared to the best available software implementation, included in the NIST submission package. The speed-ups for encryption were 2.4 and 3.9, depending on the selected parameter set. For decryption, the corresponding speed-ups were 4.0 and 6.8. In addition, for the polynomial multiplication operation itself, the speed up was in excess of 75. Our code for the NTRUEncrypt polynomial multiplier accelerator is being made open-source for further evaluation on multiple software/hardware platforms.

关键词： Post-Quantum Cryptography lattice-based NTRU hardware/software codesign High-Level Synthesis

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Automating application-driven customization of ASIPs: A survey

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JOURNAL OF SYSTEMS ARCHITECTURE 2024年 148卷

作者： Hussein, Eslam Waschneck, Bernd Mayr, Christian Infineon Technol Dresden GmbH & Co KG Konigsbrucker Str 180 D-01099 Dresden Saxony Germany Tech Univ Dresden Mommsenstr 12 Dresden Germany

The rapid advancements and stringent requirements of modern embedded computing systems have led to a surge in the demand for customized processors that can efficiently cater to specific application needs. This survey paper delves into the realm of automating application -driven customization of extensible processors, offering insights into the challenges, advancements, and trends in this domain. It explores the trade-offs between fine-grained and coarse -grained customization, discussing Custom Instructions (CIs) identification and optimization techniques, while emphasizing the shift towards larger accelerators that target complex control sequences in the application. It scrutinizes the balance between speedup and reusability, addressing the challenges of efficient design approaches to manage area and power consumption. The agile nature of early Design Space Exploration (DSE) is discussed, where rapid evaluation of area and communication costs plays a pivotal role. In essence, this survey serves as a valuable guide for researchers and practitioners in the field of processor customization, aiding designers in navigating this complex landscape to optimize performance in a rapidly evolving computing paradigm.

关键词： Extensible processors RISC ISA Custom instructions Custom accelerators Application-specific functional units Resource sharing hardware/software codesign Design space exploration

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Accelerating WebAssembly Interpreters in Embedded Systems Through hardware-Assisted Dispatching 37th

Accelerating WebAssembly Interpreters in Embedded Systems Th...

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37th International Conference on Architecture of Computing Systems (ARCS)

作者： Rupp, Matthias Schroeter, Jonathan Wallentowitz, Stefan Hsch Munchen Univ Appl Sci Dept Comp Sci & Math Munich Germany

ISBN: (纸本)9783031661457;9783031661464

WebAssembly is a promising bytecode virtualization technology for embedded systems. WebAssembly interpreters for embedded demonstrate strong isolation and portability. However, they come with a significant performance penalty compared to direct bare-metal execution or compiled WebAssembly code. This creates demand for interpreter optimization. In this work, we present an approach that increases the execution speed of interpreted WASM code by offloading computed GOTOs, as used in interpreters, to a hardware accelerator. We describe the accelerator's hardware design, as well as the integration in the popular WebAssembly Micro Runtime (WAMR). To prove the functionality and effectiveness of our approach, we integrate the accelerator into an open-source RISC-V processor core and evaluate WASM interpretation using different benchmarks. Our results show that the approach significantly increases execution speed while only creating minimal code size overhead. Finally, we give an outlook on possible future improvements of the accelerator.

关键词： WebAssembly RISC-V Interpreter Accelerator hardware/software codesign Computed GoTo

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A Lightweight and Efficient ECDSA Core for FPGA-Based Edge-AI Platforms

A Lightweight and Efficient ECDSA Core for FPGA-Based Edge-A...

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4th International Conference on Advanced Research in Technologies Information Innovation and Sustainability-ARTIIS-Annual

作者： Cuong Pham-Quoc Ho Chi Minh City Univ Technol HCMUT 268 Ly Thuong Kiet StDist 10 Ho Chi Minh City Vietnam Vietnam Natl Univ Ho Chi Minh City VNU HCM Ho Chi Minh City Vietnam

ISBN: (纸本)9783031834318;9783031834325

Data security and integrity are crucial across various domains, particularly in Edge-AI applications like healthcare and intelligent systems. Security concerns intensify when deploying AI at the edge due to sensitive data being processed locally rather than in cloud services. Cryptographic algorithms are usually employed on Edge-AI platforms to ensure data integrity and protect confidential data. Among the most effective approaches for developing digital signature algorithms (DSA), elliptic curve cryptography (ECC) stands out. In our research, we designed and implemented a dedicated hardware computing core for DSA using the ECDSA algorithm. This core accelerates processing throughput on FPGA-based edge-AI platforms. We implemented the proposed system on an Edge-AI platform powered by a Xilinx FPGA Zynq UltraScale+ chip called Kria KV260. Experimental results, using a dataset certified by the National Institute of Standards and Technology (NIST), demonstrate that throughput by up to 1,680 signatures per second and 1.23 Mbps have been achieved with the prototype system.

关键词： FPGA-based Edge-AI hardware/software codesign ECC ECDSA Edge Computing IoTs

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Explainable-DSE: An Agile and Explainable Exploration of Efficient HW/SW codesigns of Deep Learning Accelerators Using Bottleneck Analysis 28

Explainable-DSE: An Agile and Explainable Exploration of Eff...

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28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

作者： Dave, Shail Nowatzki, Tony Shrivastava, Aviral Arizona State Univ Tempe AZ 85287 USA Univ Calif Los Angeles Los Angeles CA USA

ISBN: (纸本)9798400703942

Effective design space exploration (DSE) is paramount for hardware/software codesigns of deep learning accelerators that must meet strict execution constraints. For their vast search space, existing DSE techniques can require excessive trials to obtain a valid and efficient solution because they rely on black-box explorations that do not reason about design inefficiencies. In this paper, we propose Explainable-DSE - a framework for the DSE of accelerator codesigns using bottleneck analysis. By leveraging information about execution costs from bottleneck models, our DSE is able to identify bottlenecks and reason about design inefficiencies, thereby making bottleneck-mitigating acquisitions in further explorations. We describe the construction of bottleneck models for DNN accelerators. We also propose an API for expressing domain-specific bottleneck models and interfacing them with the DSE framework. Acquisitions of our DSE systematically cater to multiple bottlenecks that arise in executions of multi-functional workloads or multiple workloads with diverse execution characteristics. Evaluations for recent computer vision and language models show that Explainable-DSE mostly explores effectual candidates, achieving codesigns of 6x lower latency in 47x fewer iterations vs. non-explainable DSEs using evolutionary or ML-based optimizations. By taking minutes or tens of iterations, it enables opportunities for runtime DSEs.

关键词： design space exploration domain-specific architectures gray-box optimization bottleneck model hardware/software codesign explainability machine learning and systems

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