This research aims at hardware implementation of the reversible logic gate models and reversible logic circuit in VHDL. The application of the research pertains to the field of mathematics and cybersecurity. Furthermo...
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This research aims at hardware implementation of the reversible logic gate models and reversible logic circuit in VHDL. The application of the research pertains to the field of mathematics and cybersecurity. Furthermore, this research discusses the possibilities of changing the traditional digital logic gates, which allow the information to flow only in one direction, and successfully implementing a reverse information flow in hardware. Reversible logic gates are designed in such a way that they deduce information based on the given state of inputs and outputs. VHDL codes and simulations for reversible logic gates are introduced in this study. After developing reversible logic gates, a reversible half adder digital circuit was constructed. This implementation can be very useful for designing other larger digital circuits in the near future as it presents a new model of reversibility. To better understand the necessity of internal core architecture while designing the system, a performance analysis of the reversible half adder circuit is given. It discusses all the steps introduced inside the reversible digital architecture. Based on the simulation results, we can conclude that reversible logic gates successfully deduce information. Thus, the hardware implementation of an algorithm written in Python (high-level language) to a VHDL (low-level language) was successful. However, reversible half adder circuit simulation shows more information is needed for the reversible logic gates to become a feasible method aimed at designing complex circuits.
In this paper, an Ultra High Frequency (UHF) base band processor for a passive tag is presented. It proposes a Radio Frequency Identification (RFID) tag digital base band architecture which is compatible with the EPC ...
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In this paper, an Ultra High Frequency (UHF) base band processor for a passive tag is presented. It proposes a Radio Frequency Identification (RFID) tag digital base band architecture which is compatible with the EPC C C2/ISO18000-6B protocol. Several design approaches such as clock gating technique, clock strobe design and clock management are used. In order to reduce the area Decimal Matrix Code (DMC) technique is used. The digital base band processor has been simulated and implemented using Xilinx platform. The complete design is verified and tested on Spartan-6 Field Programmable Gate Array (FPGA) board. The performance of system is measured in terms of power. The synthesis result shows that, the power required for complete design of digital baseband processor is 5mW on a supply voltage of 1.2 V.
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