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PEAS-I - A hardware software codesign SYSTEM FOR ASIP DEVELOPMENT

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1994年第3期E77A卷 483-491页

作者： SATO, J ALOMARY, AY HONMA, Y NAKATA, T SHIOMI, A HIKICHI, N IMAI, M Tsuruoka Natl Coll of Technology Tsuruoka-shi Japan

This paper describes the current implementation and experimental results of a hardware/software codesign system for ASIP (Application Specific Integrated Processor) development: the PEAS-I System. The PEAS-I system accepts a set of application programs written in C language, associated data set, module database, and design constraints such as chip area and power consumption. The system then generates an optimized CPU core design in the form of an HDL as well as a set of application program development tools such as a C compiler, an assembler and a simulator. Another important feature of the PEAS-I system is that the system is able to give accurate estimations of chip area and performance before the detailed design of the ASIP is completed. According to the experimental results, the PEAS-I system has been found to be highly effective and efficient for ASIP development.

关键词： ASIP hardware software codesign PEAS-I CPU CORE DESIGN AUTOMATION APPLICATION PROGRAM DEVELOPMENT TOOL GENERATION

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FPGA-based Experiment Platform for hardware-software codesign and hardware Emulation

FPGA-based Experiment Platform for Hardware-Software Codesig...

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作者： Yajuvendra Nagaonkar Brigham Young University

学位级别：硕士

An FPGA-based experiment platform for hardware-software codesign experiments was developed. The proposed platform would be used by an engineer who can be affiliated with academia, research or industry for codesign experiments or hardware emulation. The platform utilizes a combination of a microcontroller and a FPGA device to enable sufficient flexibility in exploring the design space to implement codesign experiments. The FPGA device operation is integrated with that of the microcontroller to provide an overall embedded solution for codesign experimentations. It is anticipated that the platform will be used in academia for educating the students the concepts of computer architecture and microprocessor design. Future work suggested includes development of performance metrics of hardware and software solutions, and in the partitioning stage of the codesign flow.

关键词： FPGA hardware software codesign computer architecture prototyping education

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Crosstalk- and SEU-aware networks on chips

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IEEE DESIGN & TEST OF COMPUTERS 2007年第4期24卷 340-350页

作者： Frantz, Arthur Pereira Cassel, Maico Kastensmidt, Fernanda Lima Cota, Erika Carro, Luigi Univ Fed Rio Grande do Sul Inst Informat PPGC BR-91501970 Porto Alegre RS Brazil Univ Fed Rio Grande do Sul Dept Comp Sci Porto Alegre RS Brazil

This article proposes the use of mixed hardware-software solutions to simultaneously address crosstalk faults and single-event upsets in on-chip networks. After analyzing the susceptibility of routers to these faults, the authors propose a software-based solution to deal with SEUs. But they show that the effect of crosstalk faults can be corrected only through hardware-based solutions. The authors then discuss four approaches that combine the use of hardware and software mitigation techniques to simultaneously deal with SEU and crosstalk effects in NoC routers. Experimental results show that the mixed hardware-software strategy is a cost-effective solution, even in high soft-error-rate environments.

关键词： Network On Chip Single Event Upset Crosstalk Fault Tolerance Energy Aware Systems hardware software codesign

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AutoML for Architecting Efficient and Specialized Neural Networks

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IEEE MICRO 2020年第1期40卷 75-82页

作者： Cai, Han Lin, Ji Lin, Yujun Liu, Zhijian Wang, Kuan Wang, Tianzhe Zhu, Ligeng Han, Song MIT Dept Elect Engn & Comp Sci Cambridge MA 02139 USA MIT HAN Lab 77 Massachusetts Ave Cambridge MA 02139 USA

Efficient deep learning inference requires algorithm and hardware codesign to enable specialization: we usually need to change the algorithm to reduce memory footprint and improve energy efficiency. However, the extra degree of freedom from the neural architecture design makes the design space much larger: it is not only about designing the hardware architecture but also codesigning the neural architecture to fit the hardware architecture. It is difficult for human engineers to exhaust the design space by heuristics. We propose design automation techniques for architecting efficient neural networks given a target hardware platform. We investigate automatically designing specialized and fast models, auto channel pruning, and auto mixed-precision quantization. We demonstrate that such learning-based, automated design achieves superior performance and efficiency than the rule-based human design. Moreover, we shorten the design cycle by 200x than previous work, so that we can afford to design specialized neural network models for different hardware platforms.

关键词： Electronic Engineering Computing hardware software codesign Inference Mechanisms Learning Artificial Intelligence Neural Net Architecture Efficiency Deep Learning Inference Specialized Neural Network Efficiency Neural Network Auto ML Energy Efficiency hardware codesign Design Cycle Rule Based Human Design Automated Design Learning Based Auto Mixed Precision Quantization Auto Channel Pruning hardware Architecture Neural Architecture Design hardware Computer Architecture Graphics Processing Units Neural Networks Quantization Signal Computational Modeling Auto ML Neural Architecture Search Channel Pruning Mixed Precision Quantization Specialization Efficient Inference

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ASIP approach for implementation of H.264/AVC

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2008年第1期50卷 53-67页

作者： Kim, Sung Dae Sunwoo, Myung H. Ajou Univ Sch Elect & Comp Engn Suwon 442749 South Korea

This paper presents an Application Specific Instruction Set Processor (ASIP) for implementation of H.264/AVC, called Video Specific Instruction-set Processor (VSIP). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has coprocessors for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The proposed VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. Moreover, the proposed hardware accelerators have small size, consume low power consumption, and thus, they can support real-time video processing. VSIP has been thoroughly verified using an FPGA board having the Xilinx(TM) Virtex II. VSIP can implement a real-time H.264/AVC decoder. The proposed VSIP is one of promising solutions for video signal processing.

关键词： application specific instruction-set processor hardware software codesign H.264/AVC low power design data reuse hardware accelerator

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Fault models and test generation for hardware-software covalidation

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IEEE DESIGN & TEST OF COMPUTERS 2003年第4期20卷 40-47页

作者： Harris, IG Univ Calif Irvine Sch Informat & Comp Sci Irvine CA 92697 USA

Editor's note: Mixed hardware-software systems constitute a strong paradigm shift for system validation. The main barriers to overcome are finding the right fault models and optimizing the validation flow. This ar... 详细信息

关键词： Optimisation hardware software codesign Automatic Test Pattern Generation Fault Diagnosis hardware software Covalidation Mixed hardware software Systems Automatic Test Generation Optimisation Control Data Flow Fault Models Textual Fault Models Gate Level Fault Models Application Specific Fault Models System Testing hardware software Testing Refining Fault Detection Automatic Testing Application software Costs software Design Process Design

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A safe, accurate intravenous infusion control system

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IEEE MICRO 1998年第5期18卷 12-21页

作者： Barros, E dos Santos, MVD Univ Fed Pernambuco Dept Informat BR-50740940 Recife PE Brazil

This fault-tolerant system implemented in hardware and software and partitioned with a codesign methodology revolutionizes traditional IV infusion control systems.

关键词： Fault Tolerance FPG As Control Systems hardware software codesign

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Impact of system partitioning on test cost

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IEEE DESIGN & TEST OF COMPUTERS 1997年第1期14卷 64-74页

作者： AlHayek, G LeTraon, Y Robach, C LSR-IMAG

Well known as an important influence on other parts of a design, hardware-software partitioning also significantly affects test cost. This article provides a method of measuring partitioning's impact based on the cost to test each unit-level component. An Aerospatiale case study illustrates the use of this method as a design criterion.

关键词： hardware software codesign Design Partitioning Test Economics codesign Test Economics

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Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom Instructions

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2015年第3期34卷 483-494页

作者： Giaquinta, Emanuele Mishra, Anadi Pozzi, Laura Aalto Univ Dept Comp Sci & Engn Espoo 00076 Finland Univ Lugano Dept Comp Sci CH-6900 Lugano Switzerland

Automatic identification of custom instructions (CI) is the process of supporting the programmer in choosing automatically beneficial parts of the application source code that can then be synthesized and run on dedicated hardware. Identification is typically modeled as choosing a subgraph from a graph, representing the application, that has the highest speedup potential when implemented in custom hardware, and that fulfills the constraints of convexity and of a given maximum number of inputs and outputs. Existing algorithms for CI identification either enumerate all the valid subgraphs under the constraints of convexity and I/O, or return the subset of all maximal valid subgraphs with respect to convexity only. The downside of the former approach is that enumerating all valid subgraphs is costly, especially for large values of input and output constraints, while we may be interested in the subgraphs which obtain the best speedup only. Instead, the latter approach may fail to find a feasible solution, since the valid subgraphs with respect to convexity only can be too large to be useful. In this paper, we present a novel approach which attempts to fill the gap between the existing methods. In particular, we present an algorithm that enumerates the subset of all maximum valid subgraphs with respect to convexity and number of inputs and outputs. Our method revisits and combines the existing approaches and yields an algorithm which is effective and outperforms the state-of-the-art for large values of input and output constraints.

关键词： Application specific processors customizable processors hardware software codesign

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Multilevel testing for design verification of embedded systems

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IEEE DESIGN & TEST OF COMPUTERS 2002年第2期19卷 60-69页

作者： Schulz, S Rozenblit, JW Buchenrieder, KJ Nokia Irving TX 75062 USA Univ Arizona Tucson AZ 85721 USA

A multilevel testing approach for embedded systems addresses mixed hardware and software implementations. Contrary to conventional approaches, it provides consistent generation of scenarios throughout all levels of testing, an early assessment of alternative design implementations, integrated system and component testing, and performance assessments of design specifications starting from the system level.

关键词： hardware software codesign Embedded Systems Program Testing Formal Verification Formal Specification Design Specifications Multilevel Testing Embedded Systems Mixed hardware software Implementations Design Verification Consistent Scenario Generation Component Testing System Testing Performance Assessments System Testing Embedded System software Testing hardware Embedded software Prototypes Computational Modeling Computer Architecture software Prototyping Refining

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