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hardware prefetching Tuning Method Based on Program Phase Behavior

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2024年第9期33卷 2450158-2450158页

作者： Huang, Liangming Yan, Li Wu, Tiebin Jiangnan Inst Comp Technol Wuxi Peoples R China

Modern high-performance processor systems universally employ hardware prefetch engines to address the "memory wall" issue. Nonetheless, prefetchers are typically activated with the default configuration at system startup, and this fixed configuration does not always achieve the intended performance in the face of varied programs and may even degrade performance. As a result, it is crucial to investigate the prefetch configuration tuning method that adapts to different program characteristics in order to take full advantage of hardware prefetching. In this study, a hardware prefetching tuning method based on program phase behavior is proposed to determine the prefetch configuration that maximizes the overall predicted performance of the program through low-overhead online profiling. In the profiling process, the branch instruction vector sampled by the hardware performance counter is used to dynamically classify the program phase behavior, and the performance profiling is performed for each type of phase. Simultaneously, the recurring program phases are no longer profiled to reduce overhead. Following the profiling, the prefetch configuration with the best predicted performance is derived by combining the performance data from each phase and its running time proportion. The results of the tests on prefetch-sensitive programs in SPEC2006, NPB, and PARSEC demonstrate that the prefetch configuration obtained using the suggested method has a geometric average performance improvement of 7.34% over the default configuration and achieves 99.34% of the optimal configuration. Furthermore, the profiling run adds only 2.24% extra overhead as compared to the default configuration.

关键词： hardware prefetching program phase behavior dynamic profiling performance optimization overhead control

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Bouquet of Instruction Pointers: Instruction Pointer Classifier-based Spatial hardware prefetching 20

Bouquet of Instruction Pointers: Instruction Pointer Classif...

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47th ACM/IEEE Annual International Symposium on Computer Architecture (ISCA)

作者： Pakalapati, Samuel Panda, Biswabandan Intel Technol Private Ltd Birla Inst Technol & Sci Hyderabad India Indian Inst Technol Kanpur Dept Comp Sci & Engn Kanpur Uttar Pradesh India

ISBN: (纸本)9781728146614

hardware prefetching is one of the common off-chip DRAM latency hiding techniques. Though hardware prefetchers are ubiquitous in the commercial machines and prefetching techniques are well studied in the computer architecture community, the "memory wall" problem still exists after decades of micro-architecture research and is considered to be an essential problem to solve. In this paper, we make a case for breaking the memory wall through data prefetching at the L1 cache. We propose a bouquet of hardware prefetchers that can handle a variety of access patterns driven by the control flow of an application. We name our proposal Instruction Pointer Classifier based spatial prefetching (IPCP). We propose IPCP in two flavors: (i) an L1 spatial data prefetcher that classifies instruction pointers at the L1 cache level, and issues prefetch requests based on the classification, and (ii) a multi-level IPCP where the IPCP at the L1 communicates the classification information to the L2 IPCP so that it can kick-start prefetching based on this classification done at the L1. Overall, IPCP is a simple, lightweight, and modular framework for L1 and multi-level spatial prefetching. IPCP at the L1 and L2 incurs a storage overhead of 740 bytes and 155 bytes, respectively. Our empirical results show that, for memory-intensive single-threaded SPEC CPU 2017 benchmarks, compared to a baseline system with no prefetching, IPCP provides an average performance improvement of 45.1%. For the entire SPEC CPU 2017 suite, it provides an improvement of 22%. In the case of multi-core systems, IPCP provides an improvement of 23.4% (evaluated over more than 1000 mixes). IPCP outperforms the already high-performing state-of-the-art prefetchers like SPP with PPF and Bingo by demanding 30X to 50X less storage.

关键词： hardware prefetching Caching

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A hardware prefetching Mechanism for Vector Gather Instructions 9

A Hardware Prefetching Mechanism for Vector Gather Instructi...

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9th IEEE/ACM Workshop on Irregular Applications - Architectures and Algorithms (IA3)

作者： Takayashiki, Hikaru Sato, Masayuki Komatsu, Kazuhiko Kobayashi, Hiroaki Tohoku Univ Grad Sch Informat Sci Sendai Miyagi Japan Tohoku Univ Cybersci Ctr Sendai Miyagi Japan

ISBN: (纸本)9781728159874

Vector gather instructions are responsible for handling indirect memory accesses in vector processing. Since the indirect memory accesses usually express irregular access patterns, they have relatively low spatial and temporal locality compared with regular access patterns. As a result, an application with many vector gather instructions suffers from long latencies of the indirect memory accesses. Thus, the long latencies cause a significant performance degradation in vector processing. This paper proposes a hardware prefetching mechanism to hide memory access latencies of indirect memory accesses. The mechanism prefetches cacheable index data before executing a vector gather instruction, and predicts the addresses of the memory requests issued by the vector gather instruction. The mechanism then tries to prefetch the data based on the predicted addresses. As a result, the mechanism can reduce the memory access latencies of vector gather instructions. Moreover, this paper discusses how many cache blocks should be loaded per prediction regarding a single vector gather instruction by varying the prefetching parameters of distance and degree. In the evaluation, the performance of a simple kernel is examined with two types of index data: sequential and random. The evaluation results show that the prefetching mechanism improves the performance of the sequential-indexed and random-indexed kernels by 2.2x and 1.2x, respectively.

关键词： Vector instructions Indirect memory access hardware prefetching

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MTB-Fetch: Multithreading Aware hardware prefetching for Chip Multiprocessors

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER ARCHITECTURE LETTERS 2018年第2期17卷 175-178页

作者： AlBarakat, Laith M. Gratz, Paul, V Jimenez, Daniel A. Texas A&M Univ Dept Elect & Comp Engn College Stn TX 77843 USA Texas A&M Univ Dept Comp Sci & Engn College Stn TX 77843 USA

To fully exploit the scaling performance in Chip Multiprocessors, applications must be divided into semi-independent processes that can run concurrently on multiple cores within a system. One major class of such applications, shared-memory, multi-threaded applications, requires programmers insert thread synchronization primitives (i.e., locks, barriers, and condition variables) in their critical sections to synchronize data access between processes. For this class of applications, scaling performance requires balanced per-thread workloads with little time spent in critical sections. In practice, however, threads often waste significant time waiting to acquire locks/barriers in their critical sections, leading to thread imbalance and poor performance scaling. Moreover, critical sections often stall data prefetchers that mitigate the effects of long critical section stalls by ensuring data is preloaded in the core caches when the critical section is complete. In this paper we examine a pure hardware technique to enable safe data prefetching beyond synchronization points in CMPs. We show that successful prefetching beyond synchronization points requires overcoming two significant challenges in existing prefetching techniques. First, we find that typical data prefetchers are designed to trigger prefetches based on current misses. This approach this works well for traditional, continuously executing, single-threaded applications. However, when a thread stalls on a synchronization point, it typically does not produce any new memory references to trigger a prefetcher. Second, even in the event that a prefetch were to be correctly directed to read beyond a synchronization point, it will likely prefetch shared data from another core before this data has been written. While this prefetch would be considered "accurate" it is highly undesirable, because such a prefetch would lead to three extra "ping-pong" movements back and forth between private caches in the producing and con

关键词： Chip multiprocessor hardware prefetching multi-threading shared memory

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Memory Centric hardware prefetching in Multi-core Processors

Memory Centric Hardware Prefetching in Multi-core Processors

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International Standard Conference on Trustworthy Computing and Services (ISCTCS)

作者： Zhu, Danfeng Wang, Rui Luan, Zhongzhi Qian, Depei Zhang, Han Cai, Jihong Beihang Univ Sch Comp Sci & Engn Beijing 100191 Peoples R China Beijing Simulat Ctr Sci & Technol Special Syst Simulat Lab Beijing Peoples R China

ISBN: (纸本)9783662474013;9783662474006

hardware prefetching is widely employed in modern processors. It has been proved that prefetching can significantly improve application's performance unless it exhibits sparse locality. Nevertheless, prefetching may result in performance degradation in CMP systems as it issues many off-chip memory requests. In this paper, we propose MCPref, a prefetching mechanism that is sensitive to the load of memory bus. Unlike traditional prefetching mechanism, MCPref opens when memory bus is starve and halts when memory bus is busy. Simulation results show that our non-feedback prefetcher design is effective in the scenario of multi-core architecture.

关键词： hardware prefetching Memory scheduling Multi-core

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Selecting the Optimal hardware prefetching Algorithm for Parallel Workloads (Abstract Only) 15

Selecting the Optimal Hardware Prefetching Algorithm for Par...

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Proceedings of the 46th ACM Technical Symposium on Computer Science Education

作者： Saami Rahman Texas State University San Marcos TX USA

ISBN: (纸本)9781450329668

prefetching is a commonly used technique of improving low-level cache usage that predicts memory requests ahead of time and thus, improves performance by hiding memory latency. Several prefetching algorithms are implemented in hardware. For example, the Intel Core2 processor has 4 different prefetchers, each of which serves a different type of data access pattern. These prefetchers are enabled by default, based on the assumption that the prefetch unit will be triggered when it can successfully prefetch data. However, we have discovered that this assumption is incorrect and can at times hurt performance by up to 11%. We present a simple and easy-to-use framework that determines which hardware-prefetching configuration should be used for a specific workload. The guiding principle of this work that sets it apart from other similar ones is that it fits well within the development process of an average programmer possessing no detailed hardware specific knowledge. For two programs in the PARSEC benchmark, on an Intel Core2 machine, our framework results in an effective speedup of 19% compared to the baseline default setting of using all available prefetchers.

关键词： hardware prefetching

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A Complexity-Effective Local Delta Prefetcher

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IEEE TRANSACTIONS ON COMPUTERS 2025年第5期74卷 1482-1494页

作者： Navarro-Torres, Agustin Panda, Biswabandan Alastruey-Benede, Jesus Ibanez, Pablo Vinals-Yufera, Victor Ros, Alberto Univ Murcia Comp Engn Dept Murcia 30100 Spain Indian Inst Technol Comp Sci & Engn Mumbai 400076 India Univ Zaragoza Comp & Syst Engn Dept Zaragoza 50018 Spain

Data prefetching is crucial for performance in modern processors by effectively masking long-latency memory accesses. Over the past decades, numerous data prefetching mechanisms have been proposed, which have continuously reduced the access latency to the memory hierarchy. Several state-of-the-art prefetchers, namely Instruction Pointer Classifier Prefetcher (IPCP) and Berti, target the first-level data cache, and thus, they are able to completely hide the miss latency for timely prefetched cache lines. Berti exploits timely local deltas to achieve high accuracy and performance. This paper extends Berti with a larger evaluation and with extra optimizations on top of the previous conference paper. The result is a complexity-effective version of Berti that outperforms it for a large amount of workloads and simplifies its control logic. The key for those advancements is a simple mechanism for learning timely deltas without the need to track the fetch latency of each cache miss. Our experiments conducted with a wide range of workloads (CVP traces by Qualcomm, SPEC CPU2017, and GAP) show performance improvements by 4.0% over a mainstream stride prefetcher, and by a non-negligible 1.4% over the previously published version of Berti requiring similar storage.

关键词： Data prefetching hardware prefetching first-level cache stride local deltas accuracy timeliness Data prefetching hardware prefetching first-level cache stride local deltas accuracy timeliness

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Tyche: An Efficient and General Prefetcher for Indirect Memory Accesses

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ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2024年第2期21卷 1-26页

作者： Xue, Feng Han, Chenji Li, Xinyu Wu, Junliang Zhang, Tingting Liu, Tianyi Hao, Yifan Du, Zidong Guo, Qi Zhang, Fuxin Chinese Acad Sci Inst Comp Technol SKLP 6 Kexueyuan Nanlu Beijing 100190 Peoples R China Univ Chinese Acad Sci 19A Yuquan Rd Beijing 100049 Peoples R China Loongson Technol Co Ltd Loongson Ind Pk Beijing 100095 Peoples R China Chinese Acad Sci Inst Comp Technol 6 Kexueyuan Nanlu Beijing 100190 Peoples R China Univ Texas San Antonio 1 UTSA Circle San Antonio TX 78249 USA

Indirect memory accesses (IMAs, i.e., A[f(B[i])]) are typical memory access patterns in applications such as graph analysis, machine learning, and database. IMAs are composed of producer-consumer pairs, where the consumers' memory addresses are derived from the producers' memory data. Due to the built-in value-dependent feature, IMAs exhibit poor locality, making prefetching ineffective. Hindered by the challenges of recording the potentially complex graphs of instruction dependencies among IMA producers and consumers, current state-of-the-art hardware prefetchers either (a) exhibit inadequate IMA identification abilities or ( b) rely on the run-ahead mechanism to prefetch IMAs intermittently and insufficiently. To solve this problem, we propose Tyche,1 an efficient and general hardware prefetcher to enhance IMA performance. Tyche adopts a bilateral propagation mechanism to precisely excavate the instruction dependencies in simple chains with moderate length (rather than complex graphs). Based on the exact instruction dependencies, Tyche can accurately identify various IMA patterns, including nonlinear ones, and generate accurate prefetching requests continuously. Evaluated on broad benchmarks, Tyche achieves an average performance speedup of 16.2% over the state-of-the-art spatial prefetcher Berti. More importantly, Tyche outperforms the state-of-the-art IMA prefetchers IMP, Gretch, and Vector Runahead, by 15.9%, 12.8%, and 10.7%, respectively, with a lower storage overhead of only 0.57 KB.

关键词： Data prefetching hardware prefetching indirect memory accesses microarchitecture

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PARS: A Pattern-Aware Spatial Data Prefetcher Supporting Multiple Region Sizes

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2024年第11期43卷 3638-3649页

作者： Lin, Yiquan Lin, Wenhai Xu, Jiexiong Chen, Yiquan Jin, Zhen Qin, Jingchang He, Jiahao Cai, Shishun Zhang, Yuzhong Wang, Zonghui Chen, Wenzhi Zhejiang Univ Coll Comp Sci & Technol Hangzhou 310027 Peoples R China Alibaba Grp Cloud Infrastruct Serv Hangzhou 310030 Peoples R China

hardware data prefetching is a well-studied technique to bridge the processor-memory performance gap. Bit-pattern-based prefetchers are one of the most promising spatial data prefetchers that achieve substantial performance gains. In bit-pattern-based prefetchers, the region size is a crucial parameter, which denotes the memory size that can be recorded by a pattern or prefetched by a prediction. However, existing bit-pattern-based prefetchers only support one fixed region size. Our experiment shows that the fixed region size cannot meet the requirements for numerous applications and leads to suboptimal performance and high hardware overhead. In this article, we propose PARS, a pattern-aware spatial data prefetcher supporting multiple region sizes. The key idea of PARS is that it supports multiple region sizes, enabling it to simultaneously enhance application performance while reducing the hardware overhead. Moreover, PARS supports dynamically switching appropriate region sizes for different patterns through an adaptive RS-switching mechanism. We evaluated PARS on numerous workloads and results show that PARS provides an average performance improvement of 40.6% over a baseline with no data prefetchers and outperforms the two state-of-the-art prefetchers Bingo by 2.1% (up to 24.4%) and Pythia by 3.9% (up to 111.2%) in the single-core system. In the four-core system, PARS outperforms Bingo by 5.0% (up to 66.0%) and Pythia by 5.4% (up to 177.9%).

关键词： Integrated circuits Bridges Design automation prefetching Switches Performance gain Spatial databases hardware Cache data prefetching hardware prefetching microarchitecture

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A Prefetch-Adaptive Intelligent Cache Replacement Policy Based on Machine Learning

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Journal of Computer Science & Technology 2023年第2期38卷 391-404页

作者：杨会静方娟蔡旻才智 Faculty of Information Technology Beijing University of TechnologyBeijing 100124China

hardware prefetching and replacement policies are two techniques to improve the performance of the memory *** prefetching hides memory latency and improves performance,interactions take place with the cache replacement policies,thereby introducing performance variability in the *** improve the accuracy of reuse of cache blocks in the presence of hardware prefetching,we propose Prefetch-Adaptive Intelligent Cache Replacement Policy(PAIC).PAIC is designed with separate predictors for prefetch and demand requests,and uses machine learning to optimize reuse prediction in the presence of *** distinguishing reuse predictions for prefetch and demand requests,PAIC can better combine the performance benefits from prefetching and replacement *** evaluate PAIC on a set of 27 memory-intensive programs from the SPEC 2006 and SPEC *** single-core configuration,PAIC improves performance over Least Recently Used(LRU)replacement policy by 37.22%,compared with improvements of 32.93%for Signature-based Hit Predictor(SHiP),34.56%for Hawkeye,and 34.43%for *** the four-core configuration,PAIC improves performance over LRU by 20.99%,versus 13.23%for SHiP,17.89%for Hawkeye and 15.50%for Glider.

关键词： hardware prefetching machine learning Prefetch-Adaptive Intelligent Cache Replacement Policy(PAIC) replacement policy

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