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On the interactions between ILP and TLP with hardware transactional memory

MICROPROCESSORS AND MICROSYSTEMS 2024年 104卷

作者： Nicolas-Conesa, Victor Titos-Gil, Ruben Fernandez-Pascual, Ricardo Ros, Alberto Acacio, Manuel E. Univ Murcia Comp Engn Dept Murcia 30100 Spain

hardware implementations of transactional memory (HTM) are designed to facilitate efficient thread synchronization in parallel programs, encouraging the use of larger critical sections. By employing optimistic concurrency control to execute transactions speculatively, HTM systems promise to deliver the performance benefits typically associated with fine-grained locks. In doing so, HTM systems must deal with transaction aborts. While under certain conditions aborts may be caused by the inherent limitations of hardware structures employed to implement TM (e.g., caches), conflicting concurrent accesses to shared memory locations are generally the prevailing cause for squashing the work done by a transaction In this study, we present what we believe to be, to the best of our knowledge, the first characterization of how the aggressiveness of processor cores, particularly their ability to exploit instruction-level parallelism (ILP), interacts with the support for optimistic thread-level speculation offered by HTM systems. We have observed that by adjusting the size of structures that facilitate out-of-order and speculative execution, the number of aborts in the execution of transactional workloads can be altered in best-effort HTM implementations. Our findings indicate that in scenarios with high contention, a smaller number of powerful cores is more suitable, whereas in low contention scenarios, using a larger number of less aggressive cores is preferable. In addition, HTM systems that employ lazy detection and those employing eager detection with requester-stalls resolution, benefit from using simpler cores. In conclusion, abort ratios can be reduced with a careful choice of both processor aggressiveness and design aspects for each application depending on its contention.

关键词： hardware transactional memory Out-of-order and speculative execution Multicore Characterization

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LockillerTM: Enhancing Performance Lower Bounds in Best-Effort hardware transactional memory 38

LockillerTM: Enhancing Performance Lower Bounds in Best-Effo...

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International Parallel and Distributed Processing Symposium (IPDPS)

作者： Wan, Li Chao, Fu Li, Qiang Han, Jun Fudan Univ State Key Lab Integrated Chips & Syst Shanghai 201203 Peoples R China

ISBN: (纸本)9798350387117;9798350387124

Concurrent access to shared data has always been a challenge for developing multi-threaded programs and a bottleneck in the performance of Chip-Multiprocessor (CMP) systems. The challenge has been exacerbated by the need to augment processor cores and network bandwidth to fulfill the low-latency demands of ever-expanding data processing. Existing commercial best-effort hardware transactional memory (HTM) is a common and effective solution. However, its architectural constraints prevent transactions from surviving in exceptions, cache overflow, and coexisting with a non-speculation fallback path, leading to unstable performance and diminishing favor. In this paper, we propose three lightweight mechanisms designed to mitigate the limitations of the best-effort HTM architecture to enhance performance stability. One is the recovery mechanism that supports the dynamic revocation of toxic conflicting requests, dramatically reducing the potential of livelocks. The second is the HTMLock mechanism with hardware and software co-design, which allows transactions using HTM and locks to run concurrently except when encountering actual conflict. Lastly, the switchingMode mechanism enables a running transaction to proactively attempt to switch to HTMLock mode in the event of a non-conflict-induced abort. Gem5 infrastructure is extended to validate and evaluate our mechanisms in a 32-core tiled CMP system. Experimental studies show that LockillerTM outperforms the coarse-grained locking scheme under STAMP benchmarks except for the yada workload, irrespective of thread number and cache size. Furthermore, our approach achieves an average of 1.86x and 1.57x speedup in all benchmarks and different threads under a typical cache size and a maximum of 7.79x and 6.73x speedup in high-contention benchmarks under extreme scenarios with only 8KB L1 cache and 32 threads, compared to best-effort HTM and state-of-the-art HTM respectively.

关键词： Concurrent control hardware transactional memory coherence protocol

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Protecting Private Keys of Dilithium Using hardware transactional memory 1

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26th International Conference on Information Security (ISC)

作者： Meng, Lingjia Fu, Yu Zheng, Fangyu Ma, Ziqiang Wang, Mingyu Ye, Dingfeng Lin, Jingqiang Chinese Acad Sci Inst Informat Engn State Key Lab Informat Secur Beijing 100085 Peoples R China Univ Chinese Acad Sci Sch Cyber Secur Beijing 100049 Peoples R China Univ Sci & Technol China Sch Cyber Secur Hefei 230027 Anhui Peoples R China Univ Chinese Acad Sci Sch Cryptol Beijing 100049 Peoples R China Ningxia Univ Sch Informat Engn Yinchuan 750021 Ningxia Peoples R China

ISBN: (数字)9783031491870

ISBN: (纸本)9783031491863;9783031491870

The confidentiality of cryptography keys is necessary in cryptographic implementations. In order to resist memory disclosure attacks that steal sensitive variables such as private keys, various schemes are proposed to implement RSA and ECDSA. Meanwhile, with the migration towards post-quantum cryptography, Dilithium has been considered as the most potential signature algorithm. It involves more and larger sensitive variables, so that existing solutions for traditional cryptographic primitives are unapplicable. In this paper, we employ hardware transactional memory (HTM) to construct the secure environment for Dilithium signing operations, protecting private keys and all other sensitive variables against memory disclosure attacks. Based on the comprehensive sensitivity analysis of variables in the Dilithium algorithm, we restrict the whole sensitive operations in transactional execution regions and adopt the transaction-splitting technology for efficiency. We implemented the prototype using Intel TSX, demonstrating its security against memory disclosure attacks and acceptable performance overheads. For example, the security-enhancement implementation of Dilithium3, which is recommended by NIST, achieves a factor of 0.75 compared to the throughput of reference implementations.

关键词： Dilithium Protection hardware transactional memory memory disclosure attacks

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Analysing software prefetching opportunities in hardware transactional memory

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JOURNAL OF SUPERCOMPUTING 2022年第1期78卷 919-944页

作者： Shimchenko, Marina Titos-Gil, Ruben Fernandez-Pascual, Ricardo Acacio, Manuel E. Kaxiras, Stefanos Ros, Alberto Jimborean, Alexandra Uppsala Univ Dept Comp Syst Uppsala Sweden Univ Murcia Comp Engn Dept Murcia Spain

hardware transactional memory emerged to make parallel programming more accessible. However, the performance pitfall of this technique is squashing speculatively executed instructions and re-executing them in case of aborts, ultimately resorting to serialization in case of repeated conflicts. A significant fraction of aborts occurs due to conflicts (concurrent reads and writes to the same memory location performed by different threads). Our proposal aims to reduce conflict aborts by reducing the window of time during which transactional regions can suffer conflicts. We achieve this by using software prefetching instructions inserted automatically at compile-time. Through these prefetch instructions, we intend to bring the necessary data for each transaction from the main memory to the cache before the transaction itself starts to execute, thus converting the otherwise long latency cache misses into hits during the execution of the transaction. The obtained results show that our approach decreases the number of aborts by 30% on average and improves performance by up to 19% and 10% for two out of the eight evaluated benchmarks. We provide insights into when our technique is beneficial given certain characteristics of the transactional regions, the advantages and disadvantages of our approach, and finally, discuss potential solutions to overcome some of its limitations.

关键词： hardware transactional memory Parallel programming Compiler Software prefetching

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LosaTM: A hardware transactional memory Integrated With a Low-Overhead Scenario-Awareness Conflict Manager

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2022年第12期33卷 4849-4862页

作者： Fu, Chao Wan, Li Han, Jun Fudan Univ State Key Lab ASIC & Syst Shanghai 201203 Peoples R China

The vigorous development of high compute-intensive applications has led to the demand for maximizing the concurrency of multicore processors. The best-effort hardware transactional memory(HTM) is an important technology adopted by vendors to improve the potential concurrency of multicore processors, but the HTM implementations on commercial products have some drawbacks for its simplicity and need some further optimizations to enable more exploitation of concurrency. In this article, we propose and evaluate a novel design of HTM, called LosaTM, which can provide a scenario-awareness conflict management strategy. By leveraging the proposed feature of multiple-grained coherency maintenance in the coherence protocol, LosaTM resolves most false conflicts at a half-cache-line granularity. Furthermore, we design a winner/aborter vector conflict management algorithm to improve the efficiency of LosaTM in handling friendly-fire and unfairness competition that we have newly defined. In order to coordinate these integrated conflict management strategies, a scheduling strategy is also proposed to adaptively select the appropriate management according to the specific conflict scenario. We use gem5 to simulate LosaTM in detail on an 8-core tiled CMP system, and the simulation result shows that it only causes 0.7% of the L1 cache size hardware overhead while achieving a 38% average execution time reduction on the native STAMP. The speedup also demonstrates that LosaTM outperforms the state-of-the-art designs in previous works.

关键词： hardware Coherence Program processors Optimization memory management Concurrent computing Protocols Scenario-specific conflict management strategies hardware transactional memory cache coherence protocols false sharing

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Analysis of the Interactions Between ILP and TLP With hardware transactional memory 30

Analysis of the Interactions Between ILP and TLP With Hardwa...

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30th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)

作者： Nicolas-Conesa, Victor Titos-Gil, Ruben Fernandez-Pascual, Ricardo Ros, Alberto Acacio, Manuel E. Univ Murcia Comp Architecture & Parallel Syst Grp Murcia Spain

ISBN: (纸本)9781665469586

hardware transactional memory (HTM) allows the use of transactions by programmers, making parallel programming easier and theoretically obtaining the performance of fine-grained locks. However, transactions can abort for a variety of reasons, resulting in the squash of speculatively executed instructions and the consequent lass in both performance and energy efficiency. Among the different sources of abort, conflicting concurrent accesses to the same shared memory locations from different transactions are often the prevalent cause. In this work, we characterize, for the first time to the best of our knowledge, how the aggressiveness of the cores in terms of exploiting instruction-level parallelism can interact with thread-level speculation support brought by HTM systems. We observe that altering the size of the structures that support out-of-order and speculative execution changes the number of aborts produced in the execution of transactional workloads on a best-effort HTM implementation. Our results show that a small number of powerful cores is more suitable for high-contention scenarios, whereas under low contention it is preferable to use a larger number of less aggressive cores. In addition, an aggressive core can lead to performance loss in medium-contention scenarios due to an increase in the number of aborts. We conclude that depending on contention. a careful choice over processor aggressiveness can reduce abort ratios.

关键词： hardware transactional memory Out-of-Order and Speculative Execution Multicore Characterization

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Migration in hardware transactional memory on Asymmetric Multiprocessor

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IEEE ACCESS 2021年 9卷 69346-69364页

作者： Sustran, Zivojin Protic, Jelica Univ Belgrade Sch Elect Engn Belgrade 11120 Serbia

In this paper, a system is presented which implements transactions migration to an asymmetric multiprocessor in order to decrease the probability of conflicts and improve execution performance. Applications parallelization makes programming and testing much more difficult, so the goal is to avoid putting additional burden on a programmer. Therefore, the proposed solution should be fully implemented in hardware. In the asymmetric multiprocessor that is analyzed, all cores have the same instruction set, but they are asymmetric in terms of microarchitectural properties, so that N - 1 "small'' cores are identical, while the N-th "big'' core is different, as it provides better performance and higher capacities of its units. The idea is to perform transaction migration from the "small'' core to the "big'' one, based on the history of transaction execution. The experiments were performed using a significantly upgraded Gem5 simulator and eight parallel applications from the STAMP benchmark suite. The experimental results show the speedup and the rate of successfully executed transactions for five different multiprocessor configurations, including symmetric and asymmetric multiprocessors with or without transaction migration. The improvement our algorithm achieves for suitable applications is up to 14% (10% on average) in turnaround time compared to the solutions which do not make use of asymmetry for scheduling transactions.

关键词： Shared memory algorithms multicore architectures hardware transactional memory asymmetric multiprocessor thread migration

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Performance Comparison of Speculative Taskloop and OpenMP-for-Loop Thread-Level Speculation on hardware transactional memory 21

Performance Comparison of Speculative Taskloop and OpenMP-fo...

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21st IEEE International Symposium on Parallel and Distributed Computing (ISPDC)

作者： Salamanca, Juan Sao Paulo State Univ Unesp DEMAC IGCE Sao Paulo Brazil

ISBN: (数字)9781665488020

ISBN: (纸本)9781665488020

Speculative Taskloop (STL) is a loop parallelization technique that takes the best of Task-based Parallelism and Thread-Level Speculation to speed up loops with may loop-carried dependencies that were previously difficult for compilers to parallelize. Previous studies show the efficiency of STL when implemented using hardware transactional memory and the advantages it offers compared to a typical DOACROSS technique such as OpenMP ordered. This paper presents a performance comparison between STL and a previously proposed technique that implements Thread-Level Speculation (TLS) in the for worksharing construct (FOR-TLS) over a set of loops from cbench and SPEC2006 benchmarks. The results show interesting insights on how each technique can be more appropriate depending on the characteristics of the evaluated loop. Experimental results reveal that by implementing both techniques on top of HTM, speed-ups of up to 2.41x can be obtained for STL and up to 2x for FOR-TLS.

关键词： OpenMP taskloop Thread-Level Speculation parallel for hardware transactional memory

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Understanding and Utilizing hardware transactional memory Capacity 2021

Understanding and Utilizing Hardware Transactional Memory Ca...

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20th ACM SIGPLAN International Symposium on memory Management (ISMM)

作者： Cai, Zixian Blackburn, Stephen M. Bond, Michael D. Australian Natl Univ Canberra ACT Australia Ohio State Univ Columbus OH 43210 USA

ISBN: (纸本)9781450384483

hardware transactional memory (HTM) provides a simpler programming model than lock-based synchronization. However, HTM has limits that mean that transactions may suffer costly capacity aborts. Understanding HTMcapacity is therefore critical. Unfortunately, crucial implementation details are undisclosed. In practice HTM capacity can manifest in puzzling ways. It is therefore unsurprising that the literature reports results that appear to be highly contradictory, reporting capacities that vary by nearly three orders of magnitude. We conduct an in-depth study into the causes of HTM capacity aborts using four generations of Intel's transactional Synchronization Extensions (TSX). We identify the apparent contradictions among prior work, and shed new light on the causes of HTM capacity aborts. In doing so, we reconcile the apparent contradictions. We focus on how replacement policies and the status of the cache can affect HTM capacity. One source of surprising behavior appears to be the cache replacement policies used by the processors we evaluated. Both invalidating the cache and warming it up with the transactional working set can significantly improve the read capacity of transactions across the microarchitectures we tested. A further complication is that a physically indexed LLC will typically yield only half the total LLC capacity. We found that methodological differences in the prior work led to different warmup states and thus to their apparently contradictory findings. This paper deepens our understanding of how the underlying implementation and cache behavior affect the apparent capacity of HTM. Our insights on how to increase the read capacity of transactions can be used to optimize HTM applications, particularly those with large read-mostly transactions, which are common in the context of optimistic parallelization.

关键词： hardware transactional memory CPU caches Intel transactional Synchronization Extensions

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Extending hardware transactional memory capacity via rollback-only transactions and suspend/resume POWER8 TM

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DISTRIBUTED COMPUTING 2020年第3-4期33卷 327-348页

作者： Issa, Shady Felber, Pascal Matveev, Alexander Romano, Paolo Univ Lisbon INESC ID Inst Super Tecn Lisbon Portugal Univ Neuchatel Neuchatel Switzerland MIT Cambridge MA 02139 USA

transactional memory (TM) aims at simplifying concurrent programming via the familiar abstraction of atomic transactions. Recently, Intel and IBM have integrated hardware based TM (HTM) implementations in commodity processors, paving the way for the mainstream adoption of the TM paradigm. Yet, existing HTM implementations suffer from a crucial limitation, which hampers the adoption of HTM as a general technique for regulating concurrent access to shared memory: the inability to execute transactions whose working sets exceed the capacity of CPU caches. In this article we propose P8TM, a novel approach that mitigates this limitation on IBM's POWER8 architecture by leveraging a key combination of hardware and software techniques to support different execution paths. P8TM also relies on self-tuning mechanisms aimed at dynamically switching between different execution modes to best adapt to the workload characteristics. In-depth evaluation with several benchmarks indicates that P8TM can achieve striking performance gains in workloads that stress the capacity limitations of HTM, while achieving performance on par with HTM even in unfavourable workloads.

关键词： hardware transactional memory Parallel programming Concurrency Self-tuning

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