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A hardware-friendly Lightweight Partition Decision algorithm for VVC Intra and Inter Coding

IEEE SIGNAL PROCESSING LETTERS 2025年 32卷 941-945页

作者： Zan, Zhao Huang, Leilei Chen, Shushi Zeng, Xiaoyang Fan, Yibo Fudan Univ State Key Lab Integrated Chips & Syst Shanghai 201203 Peoples R China East China Normal Univ Inst Microelect Circuits & Syst Shanghai 200241 Peoples R China

The Versatile Video Coding (VVC) standard notably enhances encoding efficiency with the Quad-Tree plus Multi-Type Tree (QTMTT) partition structure. However, the complex QTMTT tool presents substantial challenges in both software and hardware implementation. To overcome those challenges, this paper introduces a hardware-friendly partition decision algorithm for VVC intra and inter coding. Firstly, we propose a lightweight backbone network to extract partition-aware features. Secondly, we employ a Quantisation Parameter (QP) fusion network to regulate the impact of QPs on the partition structure. Additionally, we apply a top-down threshold-driven post-processing algorithm, in which improbable partition types are removed to directly derive the unique partition structure. Experiments show that our method not only exceeds the previous state-of-the-art work in BD-BR performance, but also shows sufficient hardware-friendly characteristics. To the best of our knowledge, this work is among the earliest to comprehensively discuss and implement a hardware-friendly partition decision algorithm.

关键词： Partitioning algorithms hardware Encoding Signal processing algorithms Prediction algorithms Feature extraction Complexity theory Software algorithms Convolution Software VVC QTMTT partition decision complexity reduction hardware-friendly algorithm convolutional neural network intra coding inter coding

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A NEW hardware friendly 2D-DCT HEVC COMPLIANT algorithm AND ITS HIGH THROUGHPUT AND LOW POWER hardware DESIGN 26

A NEW HARDWARE FRIENDLY 2D-DCT HEVC COMPLIANT ALGORITHM AND ...

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26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Braatz, Luciano Almeida Schneider Beck, Antonio Carlos Zatt, Bruno Agostini, Luciano Volcan Palomino, Daniel Munari Porto, Marcelo Schiavon Fed Univ Pelotas UFPel Grad Program Comp Sci PPGC Video Technol Res Grp ViTech Pelotas RS Brazil Fed Univ Rio Grande Sul UFRGS Inst Informat INF Porto Alegre RS Brazil

ISBN: (纸本)9781728109961

This paper presents a hardware-friendly algorithm to maximize the throughput of the Discrete Cosine Transform (DCT) of the High Efficiency Video Coding (HEVC), together with its hardware design. The Fast DCT (FCT) algorithm is based on the Cooley-Tuckey algorithm for the Fast Fourier Transform (FFT) with pre- and post-processing required to maintain the compliance with the HEVC. The resulting algorithm allows high throughput while maintaining low power dissipation. The designed hardware was synthesized for a 45-nm Nangate technology and it reaches a throughput of 81.28GSamples per second when consuming 12.33mW. Such energy efficiency and throughput surpass all related works in the literature.

关键词： HEVC video coding direct transform DCT hardware-friendly algorithm hardware architecture

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A Fast CABAC hardware Design for Accelerating the Rate Estimation in HEVC

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2022年第4期32卷 2385-2395页

作者： Cai, Yujie Fan, Yibo Huang, Leilei Zeng, Xiaoyang Yin, Haibing Zeng, Bing Fudan Univ Coll Microelect State Key Lab ASIC & Syst Shanghai 200433 Peoples R China Hangzhou Dianzi Univ Sch Commun Engn Hangzhou 310018 Peoples R China Univ Elect Sci & Technol China Sch Informat & Commun Engn Chengdu 610054 Peoples R China

The latest High Efficiency Video Coding standard achieves twice the coding efficiency of the H264 standard through a complex rate-distortion optimization (RDO). The coded hit-streams are produced with context adaptive binary arithmetic coding (CABAC). CABAC itself is a very time-consuming process that includes binarization, context modeling, interval subdivision, renormalization, outstanding bit handling, and context updating. The aim of this research is to speed up the CABAC process through several simplifications. First, we approximate three parts of the CABAC, i.e., interval subdivision, renormalization, and outstanding bit handling, with a piecewise-linear function that is very friendly to hardware implementation. In order to achieve better hardware parallelism, we also improve the coding process at the sub-block level. The context of syntax elements in a sub-block is redistributed to skip the complex calculation of context indexing. We perform context updating at the granularity of sub-blocks so that the data dependency of the context updating is removed completely, and the original serial encoding process is changed to a parallel encoding process. At the same time, we make another simplification for the context modeling of cu_skip_flag. Based on these simplifications, we build a parallel hardware architecture for the rate estimation of the RDO process. This architecture completes the bit estimation of a 32 x 32 coding tree unit (CTU) in 220.8 nano-seconds, whereas the Bjontegaard Delta rate increases by only 2.225%. We believe that the proposed architecture can meet the requirements of 8K@120 fps ultrahigh-definition videos. This is the first study to simplify the hardware design of rate estimation by changing the context allocation and updating rules.

关键词： HEVC rate-distortion optimization CABAC rate estimation hardware-friendly algorithm

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hardware-friendly Descreening

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IEEE TRANSACTIONS ON IMAGE PROCESSING 2010年第3期19卷 746-757页

作者： Siddiqui, Hasib Boutin, Mireille Bouman, Charles A. Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA

Conventional electrophotographic printers tend to produce Moire artifacts when used for printing images scanned from printed material such as books and magazines. We propose a novel noniterative, nonlinear, and space-variant descreening filter that removes a wide range of Moire-causing screen frequencies in a scanned document while preserving image sharpness and edge detail. This filter is inspired by Perona-Malik's anisotropic diffusion equation. The amount of diffusion of the image intensity resulting from applying the filter is governed by an edge intensity estimate that is robust under halftone noise. More precisely, the filter extracts a spatial feature vector comprising local intensity gradients estimated from a local window in a presmoothed version of the noisy input image. Tunable nonlinear polynomial functions of this feature vector are then used to perform one iteration of a discrete diffusion controlled by the intensity gradient. The polynomial functions and feature extraction kernels are selected empirically in order to minimize computation while ensuring robust performance across a wide range of test images on a target imaging platform. The algorithm uses integer arithmetic, mostly relying on low-cost bit-wise shift and addition operations, and uses a strictly sequential architecture to provide a cost-effective and robust descreening solution in practical imaging devices including copiers and multifunction printers. We compare the performance of the proposed algorithm to other descreening solutions and demonstrate that the new algorithm improves quality over the existing methods while reducing computation.

关键词： Anisotropic diffusion descreening halftone hardware-friendly algorithm Moire artifacts resolution synthesis SUSAN filter

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A Computational-Efficient Deformable Convolution Network Accelerator via hardware and algorithm Co-Optimization 36

A Computational-Efficient Deformable Convolution Network Acc...

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36th IEEE Workshop on Signal Processing Systems (SiPS)

作者： Li, Shan Cao, Shan Hui, Lanqing Jiang, Zhiyuan Sun, Yanzan Xu, Shugong Shanghai Univ Sch Commun & Informat Engn Shanghai Peoples R China

ISBN: (数字)9781665485241

ISBN: (纸本)9781665485241

Deformable convolution networks (DCNs) shows performance boosts on object recognition tasks by enabling variable geometric modeling. However, the irregular addressing of memory accesses makes it inefficient for hardware acceleration. In this paper, we propose a computational-efficient hardware accelerator for DCNs. First, a hardware-friendly DCNs inference scheme is introduced based on the original DCNs algorithm with little accuracy loss. Secondly, a hardware accelerator architecture is presented correspondingly, and an speed matching method is introduced to maximizing the number of deformable layers without latency increase. The proposed accelerator is implemented on the Arria 10 FPGA, results of which show that the proposed design achieves the highest throughput and DSP efficiency compared with state-of-the-art DCNs accelerators.

关键词： hardware accelerator hardware-friendly algorithm deformable convolution FPGA

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A hardware-friendly Method for Rate-Distortion Optimization of HEVC Intra Coding

A Hardware-Friendly Method for Rate-Distortion Optimization ...

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International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

作者： Shen, Weiwei Fan, Yibo Huang, Leilei Li, Jiali Zeng, Xiaoyang Fudan Univ State Key Lab ASIC & Syst Shanghai 200433 Peoples R China

ISBN: (纸本)9781479927760

The next generation standard of coding, High Efficiency Video Coding (HEVC) aims to provide significantly improved compression performance in comparison with all existing video coding standards, such as MPEG-4, H.263, and H.264/AVC. The tool of rate-distortion optimization (RDO) mode decision has proven to be extremely important. Due to the increase in the number of intra prediction directions and large size of coding unit (CU), prediction unit (PU) and transform unit (TU), the number involved in RDO process rises dramatically, which is an extremely timing-and-computation-consuming process. In this paper, we propose a four-pixel-strip based ESAD and quantized TU coefficients based linear model to estimate the distortion and rate part of the RD cost function respectively. Experimental results show that the proposed RD cost function provides 85.8% area reduction and 1260% throughput improvement in hardware design, with negligible loss of bitrate and PSNR.

关键词： hardware-friendly algorithm intra prediction rate-distortion optimization HEVC

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An On-Chip-Trainable Gaussian-Kernel Analog Support Vector Machine

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2010年第7期57卷 1513-1524页

作者： Kang, Kyunghee Shibata, Tadashi Univ Tokyo Sch Engn Dept Elect Engn & Informat Syst Tokyo 1130032 Japan

An analog circuit architecture of Gaussian-kernel support vector machines having on-chip training capability has been developed. It has a scalable array processor configuration and the circuit size increases only in proportion to the number of learning samples. Thanks to the hardware-friendly algorithm employed in the present work, the learning function is realized by attaching a small additional circuitry to the SVM classifying hardware. The SVM classifying hardware is composed as an array of Gaussian circuits. Although the system is inherently analog, the input and output signals including training results are all available in digital format. Therefore, the learned parameters are easily stored and reused after training sessions. A proof-of concept chip containing 2-class, 2-D, 12-template classifier was designed and fabricated in a 0.18-mu m CMOS technology. The experimental results obtained from the fabricated chips are presented and compared with theoretical calculation results. It can classify 8.7 x 10(5) vectors per second and the average power dissipation was 220 mu W. The learning capability was tested using eight fabricated chips and the variability among these chips were evaluated. Successful operation of the chips was confirmed by measurement results, which demonstrates that on-chip-learning can compensate for analog imperfections.

关键词： Analog VLSI Gaussian circuit hardware-friendly algorithm machine learning on-chip learning subthreshold circuit support vector machine

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Low latency group-sorted QR decomposition algorithm for larger-scale MIMO systems

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IET COMMUNICATIONS 2021年第12期15卷 1548-1560页

作者： Chen, Lirui Wang, Yu Xing, Zuocheng Qiu, Shikai Wang, Qinglin Li, Yongzhong Natl Univ Def Technol Natl Lab Parallel & Distributed Proc Changsha 410005 Peoples R China Changsha Univ Sch Comp Sci Changsha 410005 Peoples R China

Sorted QR decomposition (SQRD) has been extensively adopted for various multiple-input-multiple-output (MIMO) detectors, in which the sorting process incurs severe latency when it comes to larger-scale MIMO situations. This paper proposes a group-SQRD (GSQRD) algorithm to alleviate the latency problem of general SQRD architectures for larger-scale MIMO systems. Via predictively sorting a group of 4 columns at one stage, the GSQRD could eliminate the processing latency by 41% for decomposing 16x16 complex-valued matrices. Additionally, this percentage even rises up to 68% for decomposing 128x128 matrices. To analyse the side effects, the GSQRD is applied in various MIMO detectors in a simulation link, which exhibits a negligible performance degradation for MIMO detection. Moreover, GSQRD is a hardware-friendly algorithm because the division and square root operations in GSQRD are converted to multiplications for simplifying the hardware implementation. Based on this algorithm, two corresponding hardware architectures, which contains 2 and 4 columns respectively in a sorting group, are also implemented with 65-nm CMOS technology. These architectures can work at 513 MHz to decompose 16x16 complex-valued matrices. The processing latencies are respectively 0.32 and 0.26 mu s, superior to the state-of-art designs.

关键词： sorting group processing latencies sorting GSQRD algorithm signal detection hardware-friendly algorithm group-SQRD algorithm MIMO detectors square root operations matrix algebra SQRD architectures frequency 513.0 MHz low latency group-sorted QR decomposition algorithm Algebra CMOS technology MIMO detection Signal detection latency problem detector circuits multiple-input-multiple-output detectors sorting process larger-scale MIMO systems complex-valued matrices Radio links and equipment CMOS integrated circuits Modulators, demodulators, discriminators and mixers MIMO communication

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Evaluation of PNN pattern-layer activation function approximations in different training setups

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INTERNATIONAL JOURNAL OF SPEECH TECHNOLOGY 2019年第4期22卷 1039-1049页

作者： Dukov, Nikolay T. Ganchev, Todor D. Vrahatis, Michael N. Tech Univ Varna Fac Comp & Automat ASPL Varna 9010 Bulgaria Univ Patras Dept Math Computat Intelligence Lab CI Lab GR-26110 Patras Greece

The processing of inputs in the first two layers of the probabilistic neural network (PNN) is highly parallel which makes it quite appropriate for hardware implementations with FPGA. One of the main inconveniences however remains the implementation of the nonlinear activation function of the pattern layer neurons. In the present study, we investigate the applicability of three approximations of the exponential activation function with look-up tables of different precision and the effect this has on the training process and the classification accuracy. Furthermore, seeking for a highly-parallel hardware-friendly algorithm for the automated adjustment of the spread factor sigma(i), we investigated the performance of fifteen PNN training setups, which are based on the differential evolution (DE) or unified particle swarm optimization (UPSO) methods. The experimental evaluation was performed following a common experimental protocol, which makes use of the Parkinson Speech Dataset, as this research aims to support the development of portable medical devices that are capable to detect episodes with exacerbation in patients with Parkinson's disease. The performance of the most successful setups is discussed in terms of error rates and from the perspective of the resources required for an FPGA-based implementation.

关键词： Probabilistic neural network Differential evolution Particle swarm optimization Parkinson speech dataset hardware-friendly algorithm

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A Two-staged Adaptive Successive Cancellation List Decoding for Polar Codes

A Two-staged Adaptive Successive Cancellation List Decoding ...

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IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Xia, ChenYang Fan, YouZhe Tsui, Chi-Ying HKUST Dept ECE Hong Kong Peoples R China MaxLinear Carlsbad CA USA

ISBN: (纸本)9781728103976

Polar codes achieve outstanding error correction performance when using successive cancellation list (SCL) decoding with cyclic redundancy check. A larger list size brings better decoding performance and is essential for practical applications such as 5G communication networks. However, the decoding speed of SCL decreases with increased list size. Adaptive SCL (A-SCL) decoding can greatly enhance the decoding speed, but the decoding latency for each codeword is different so A-SCL is not a good choice for hardware-based applications. In this paper, a hardware-friendly two-staged adaptive SCL (TA-SCL) decoding algorithm is proposed such that a constant input data rate is supported even if the list size for each codeword is different. A mathematical model based on Markov chain is derived to explore the bounds of its decoding performance. Simulation results show that the throughput of TA-SCL is tripled for good channel conditions with negligible performance degradation and hardware overhead.

关键词： Polar codes Successive cancellation list decoding Adaptive decoding Markov chain hardware-friendly algorithm

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