This paper propose the high performance FFT architecture by minimization of power using the Multiplier less Multiple Constant Multiplication (MMCM) approach. In the recent applications, hardware engineers have continu...
详细信息
ISBN:
(纸本)9781467349215
This paper propose the high performance FFT architecture by minimization of power using the Multiplier less Multiple Constant Multiplication (MMCM) approach. In the recent applications, hardware engineers have continuously tried to design a well-organized FFT architecture in an efficient manner. In the proposed architecture has the MCM system in which the multiplier can be replaced by using the adders/subtractors and the shifts operations. The addition and shift operations that realize the complex multiplication with the help of Heuristic Cumulative Benefit (hcub) algorithm and it uses folding transformation which reduces the power consumption in the architecture. FFT architecture has a butterfly structure which act as a important part in the multiplications by constants, this can be reduced by using the MCM approach. Thus, the MCM with hcub algorithm in the butterflies can. effectively reduce the number of real as well as imaginary multiplications by constants. Thus the folded FFT hardware architectures with are widely used for low area and low power consumption overall which produce high performance architecture.
The coordinate rotation digital computer (CORDIC) is a class of shift-add algorithm for the rotation of vectors on a plane. The major problem in this CORDIC algorithm is the linear rate of convergence with the speed o...
详细信息
The coordinate rotation digital computer (CORDIC) is a class of shift-add algorithm for the rotation of vectors on a plane. The major problem in this CORDIC algorithm is the linear rate of convergence with the speed of the iteration. The main aim of the improved CORDIC algorithm is to utilise an integrated adder subtractor in place of binary adder subtractor to decrease the count of iterations and hardware reduction technique. The improved CORDIC splits the rotation angle into several series of micro-rotation angles to calculate the rotation and the new set of angle provides a fast convergence. The canonical signed-digit (CSD) approach together with hcub algorithm employs for the number of adder subtractor reduction and shifters in CORDIC architecture design. The performances of the proposed CORDIC design have been verified by employing it in FFT implementation. The simulation result indicates the higher frequency of 77.20%, 82.78%, 78.30% and 76.57% when compared with conventional methods. The evaluation of FFT is also done by comparing with the conventional methods. The power consumption, number of iterations and the hardware complexity reduced by using the improved CORDIC and the working of this proposed algorithm is evaluated through the FPGA implementation.
The coordinate rotation digital computer (CORDIC) is a shift-add algorithm used for rotating vectors in a plane. Several techniques are proposed in the literature for calculation of trigonometric functions which requi...
详细信息
ISBN:
(纸本)9781538677995
The coordinate rotation digital computer (CORDIC) is a shift-add algorithm used for rotating vectors in a plane. Several techniques are proposed in the literature for calculation of trigonometric functions which requires large memory usage. Due to the flexibility, CORDIC algorithm is best alternative and allows high quantization accuracy by maximizing word length. The linear-rate convergence creates the major problem in CORDIC algorithm with the source of word-length and iteration speed. The power consumption is also a major issues which affects the performance due to array of shift-add operations. For further improvement, in this paper, we propose a low power and high speed CORDIC design with an improved power control and hardware reduction techniques. We employ the canonical signed-digit (CSD) technique and hcub algorithm for reducing the number of shifters and adder/subtractor in the design. Then, we proposed an adder based on the advanced Boolean logic technique. These three techniques are used to redesign the entire CORDIC logic stages in [16] thereby contributing in power consumption reduction. The functionality of proposed CORDIC algorithm is assessed through FPGA implementations. The simulation result shows that the proposed method has higher frequency of 78.91%, 83.42%, 79.89% and 77.01% when compared with other architectures.
CORDIC (Coordinate Rotation Digital Computer) has been designed and implemented in many variants in the past five decades where the different architectures of the algorithm were used in many diverse applications. CORD...
详细信息
ISBN:
(纸本)9781728188768
CORDIC (Coordinate Rotation Digital Computer) has been designed and implemented in many variants in the past five decades where the different architectures of the algorithm were used in many diverse applications. CORDIC algorithm is a flexible shift and add algorithm having an important feature of reduced quantization errors in the case of higher word lengths when compared to other algorithms. The major issue with the algorithm is due to its linear rate convergence with the speed of iteration. Its overall performance is also affected due to repeated number of shift and adds operations and thereby leading to high power consumption. The main aim of this work is to use a new integrated adder and subtractor designed using reversible gates in the place of binary adders and subtractors used in the previous design. This improved CORDIC uses an architecture where the rotation angle is split into micro rotation angles, where these angle sets provides faster convergence by reducing the number of iterations. Overall performance of the proposed algorithm is implemented using variety of FPGA families like Virtex-4, Virtex-5 and Artix-7 devices with comparison to parameters like area, frequency and power consumed. It is compared with the Conventional CORDIC and LH CORDIC designs.
暂无评论