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heterogeneous programming using OpenMP and CUDA/HIP for hybrid CPU-GPU scientific applications

INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2023年第5期37卷 626-646页

作者： Tallada, Marc Gonzalez Morancho, Enric Univ Politecn Catalunya BarcelonaTECH Comp Architecture Dept Barcelona Spain Univ Politecn Catalunya BarcelonaTECH Comp Architecture Dept Jordi Girona 1-3 Barcelona 08034 Spain

Hybrid computer systems combine compute units (CUs) of different nature like CPUs, GPUs and FPGAs. Simultaneously exploiting the computing power of these CUs requires a careful decomposition of the applications into balanced parallel tasks according to both the performance of each CU type and the communication costs among them. This paper describes the design and implementation of runtime support for OpenMP hybrid GPU-CPU applications, when mixed with GPU-oriented programming models (e.g. CUDA/HIP). The paper describes the case for a hybrid multi-level parallelization of the NPB-MZ benchmark suite. The implementation exploits both coarse-grain and fine-grain parallelism, mapped to compute units of different nature (GPUs and CPUs). The paper describes the implementation of runtime support to bridge OpenMP and HIP, introducing the abstractions of Computing Unit and Data Placement. We compare hybrid and non-hybrid executions under state-of-the-art schedulers for OpenMP: static and dynamic task schedulings. Then, we improve the set of schedulers with two additional variants: a memorizing-dynamic task scheduling and a profile-based static task scheduling. On a computing node composed of one AMD EPYC 7742 @ 2.250 GHz (64 cores and 2 threads/core, totalling 128 threads per node) and 2 x GPU AMD Radeon Instinct MI50 with 32 GB, hybrid executions present speedups from 1.10x up to 3.5x with respect to a non-hybrid GPU implementation, depending on the number of activated CUs.

关键词： heterogeneous programming hybrid CPU-GPU OpenMP CUDA HIP

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heterogeneous programming and Optimization of Gyrokinetic Toroidal Code Using Directives 5th

Heterogeneous Programming and Optimization of Gyrokinetic To...

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5th International Workshop on Accelerator programming Using Directives (WACCPD)

作者： Zhang, Wenlu Joubert, Wayne Wang, Peng Wang, Bei Tang, William Niemerg, Matthew Shi, Lei Taimourzadeh, Sam Bao, Jian Lin, Zhihong Univ Calif Irvine Dept Phys & Astron Irvine CA 92697 USA Chinese Acad Sci Inst Phys Beijing Peoples R China Oak Ridge Natl Lab Oak Ridge TN USA NVidia Santa Clara CA USA Princeton Univ Princeton NJ 08544 USA IBM Corp New York NY USA

ISBN: (纸本)9783030122744;9783030122737

The latest production version of the fusion particle simulation code, Gyrokinetic Toroidal Code (GTC), has been ported to and optimized for the next generation exascale GPU supercomputing platform. heterogeneous programming using directives has been utilized to balance the continuously implemented physical capabilities and rapidly evolving software/hardware systems. The original code has been refactored to a set of unified functions/calls to enable the acceleration for all the species of particles. Extensive GPU optimization has been performed on GTC to boost the performance of the particle push and shift operations. In order to identify the hotspots, the code was the first benchmarked on up to 8000 nodes of the Titan supercomputer, which shows about 2-3 times overall speedup comparing NVidia M2050 GPUs to Intel Xeon X5670 CPUs. This Phase I optimization was followed by further optimizations in Phase II, where single-node tests show an overall speedup of about 34 times on SummitDev and 7.9 times on Titan. The real physics tests on Summit machine showed impressive scaling properties that reaches roughly 50% efficiency on 928 nodes of Summit. The GPU + CPU speed up from purely CPU is over 20 times, leading to an unprecedented speed.

关键词： Massively parallel computing heterogeneous programming Directives GPU OpenACC Fusion plasma Particle in cell

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Static Stages for heterogeneous programming

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PROCEEDINGS OF THE ACM ON programming LANGUAGES-PACMPL 2017年第OOPSLA期1卷 1-27页

作者： Sampson, Adrian McKinley, Kathryn S. Mytkowicz, Todd Cornell Univ Dept Comp Sci Gates Hall Ithaca NY 14853 USA Google 1600 Amphitheatre Pkwy Mountain View CA 94043 USA Microsoft Res 1 Microsoft Way Redmond WA 98052 USA

heterogeneous hardware is central to modern advances in performance and efficiency. Mainstream programming models for heterogeneous architectures, however, sacrifice safety and expressiveness in favor of low-level control over performance details. The interfaces between hardware units consist of verbose, unsafe APIs;hardware-specific languages make it difficult to move code between units;and brittle preprocessor macros complicate the task of specializing general code for efficient accelerated execution. We propose a unified low-level programming model for heterogeneous systems that offers control over performance, safe communication constructs, cross-device code portability, and hygienic metaprogramming for specialization. The language extends constructs from multi-stage programming to separate code for different hardware units, to communicate between them, and to express compile-time code optimization. We introduce static staging, a different take on multi-stage programming that lets the compiler generate all code and communication constructs ahead of time. To demonstrate our approach, we use static staging to implement BraidGL, a real-time graphics programming language for CPU-GPU systems. Current real-time graphics software in OpenGL uses stringly-typed APIs for communication and unsafe preprocessing to generate specialized GPU code variants. In BraidGL, programmers instead write hybrid CPU-GPU software in a unified language. The compiler statically generates target-specific code and guarantees safe communication between the CPU and the graphics pipeline stages. Example scenes demonstrate the language's productivity advantages: BraidGL eliminates the safety and expressiveness pitfalls of OpenGL and makes common specialization techniques easy to apply. The case study demonstrates how static staging can express core placement and specialization in general heterogeneous programming.

关键词： Multi-stage programming heterogeneous programming graphics programming OpenGL

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Supporting efficient overlapping of host-device operations for heterogeneous programming with CtrlEvents

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JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2023年 179卷

作者： Torres, Yuri Andujar, Francisco J. Gonzalez-Escribano, Arturo Llanos, Diego R. Univ Valladolid Dept Informat Valladolid Spain

heterogeneous systems with several kinds of devices, such as multi-core CPUs, GPUs, FPGAs, among others, are now commonplace. Exploiting all these devices with device-oriented programming models, such as CUDA or OpenCL, requires expertise and knowledge about the underlying hardware to tailor the application to each specific device, thus degrading performance portability. Higher-level proposals simplify the programming of these devices, but their current implementations do not have an efficient support to solve problems that include frequent bursts of computation and communication, or input/output operations. In this work we present CtrlEvents, a new heterogeneous runtime solution which automatically overlaps computation and communication whenever possible, simplifying and improving the efficiency of data-dependency analysis and the coordination of both device computations and host tasks that include generic I/O operations. Our solution outperforms other state-of-the-art implementations for most situations, presenting a good balance between portability, programmability and efficiency. (c) 2023 The Author(s). Published by Elsevier Inc. This is an open access article under the CC BY license (http://creativecommons .org /licenses /by /4 .0/).

关键词： Parallel programming heterogeneous programming Asynchronous operations Events GPUs

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heterogeneous multicore parallel programming for graphics processing units

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SCIENTIFIC programming 2009年第4期17卷 325-335页

作者： Bodin, Francois Bihan, Stephane CAPS Entreprise F-35000 Rennes France

Hybrid parallel multicore architectures based on graphics processing units (GPUs) can provide tremendous computing power. Current NVIDIA and AMD Graphics Product Group hardware display a peak performance of hundreds of gigaflops. However, exploiting GPUs from existing applications is a difficult task that requires non-portable rewriting of the code. In this paper, we present HMPP, a heterogeneous Multicore Parallel programming workbench with compilers, developed by CAPS entreprise, that allows the integration of heterogeneous hardware accelerators in a unintrusive manner while preserving the legacy code.

关键词： heterogeneous programming GPUs compiler runtime

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Portability efficiency approach for calculating performance portability

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FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 2025年 170卷

作者： Marowka, Ami Parallel Res Lab 8 Rosh Pina Petah Tiqwa 49729 Israel

The emergence of heterogeneity in high-performance computing, which harnesses under one integrated system several platforms of different architectures, also led to the development of innovative cross-platform programming models. Along with the expectation that these models will yield computationally intensive performance, there is demand for them to provide a reasonable degree of performance portability. Therefore, new tools and metrics are being developed to measure and calculate the level of performance portability of applications and programming models. The ultimate measure of performance portability is performance efficiency. Performance efficiency refers to the achieved performance as a fraction of some peak theoretical or practical baseline performance. Application efficiency approaches are the most popular and attractive performance efficiency measures among researchers because they are simple to measure and calculate. Unfortunately, the way they are used yields results that do not make sense, while violating one of the basic criteria that defines and characterizes the performance portability metrics. In this paper, we demonstrate how researchers currently use application efficiency to calculate the performance portability of applications and explain why this method deviates from its original definition. Then, we show why the obtained results do not make sense and propose practical solutions that satisfy the definition and criteria of performance portability metrics. Finally, we present a new performance efficiency approach called portability efficiency, which is immune to the shortcomings of application efficiency and substantially improves the aspect of portability when calculating performance portability.

关键词： Performance portability Application efficiency Portability efficiency heterogeneous programming High performance computing metric

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programming heterogeneous Systems with Array Types 15

Programming Heterogeneous Systems with Array Types

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2015 15th IEEE ACM International Symposium on Cluster Cloud and Grid Computing (CCGrid 2015)

作者： Cui, Xiang Li, Xiaowen Chen, Yifeng Peking Univ Sch EECS HCST Key Lab Beijing Peoples R China Air Def Forces Acad Zhengzhou Peoples R China State Key Lab Math Engn & Adv Comp Wuxi Peoples R China Henan Univ Coll Comp & Informat Engn Kaifeng Peoples R China

ISBN: (纸本)9781479980062

This paper describes the use of array notation called Parray in refinement of parallel programs concerning array type that separates the physical data layout and logical structure of multi-dimensional data, and the control flow diversion of heterogeneous processor units. A case study on matrix multiplication demonstrates refinement of Parray programs: the code evolves from a simple single CPU-thread code to a multi-thread code on CPU/MIC and then a GPU code by modifying the array types in only a few lines of code. A GPU-based SGEMM is implemented in Parray and achieves almost the same Gflops of CUBLAS 4.0 when testing on a single node of Tian-1A system. Because the code operates directly on the logical structure of array, the same SGEMM code can work on different physical array data layouts.

关键词： heterogeneous programming array type programming interface

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Parallel bitsliced AES through PHAST: a single-source high-performance library for multi-cores and GPUs

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JOURNAL OF CRYPTOGRAPHIC ENGINEERING 2019年第2期9卷 159-171页

作者： Peccerillo, Biagio Bartolini, Sandro Koc, Cetin Kaya Univ Siena Dipartimento Ingn Informaz & Sci Matemat Siena Italy Univ Calif Santa Barbara Dept Comp Sci Santa Barbara CA 93106 USA

PHAST library is a high-level heterogeneous STL-like C++ library that can be targeted on multi-core processors and Nvidia GPUs. It permits to exploit the performance of modern parallel architectures without the complexity of parallel programming. The library manages the programming and critical fine tuning of the parallel execution on both platforms without interfering with the application code structure, while maintaining the possibility to use architecture-specific features and instructions. In cryptography, performance and architectural efficiency of software implementations is crucial. This is witnessed by the extensive research in highly optimized and specialized versions of many protocols. In this paper, we assess the performance overhead and productivity improvement achievable through the PHAST library. We implement a pseudo random number generator (PRNG) based on cache-timing-attack resistant AES. We compare it with the fastest implementations in both CPU and Nvidia GPU domains. Achieved results show that the PHAST code is shorter and simpler than the state-of-the-art implementations. Its source length is 59.59% of the reference CUDA C implementation and 88.18% of the sequential C++ version for CPUs, despite being the same for both targets. It is also far less complex in terms of McCabe's and Halstead's metrics. Results show that these productivity improvements induce a limited performance overhead of the library layer: less than 5% on single-thread execution for CPUs and around 10% on Nvidia GPUs. Furthermore, performance of the PHAST PRNG automatically scales with the available cores in a nearly linear fashion, allowing programmers to fully exploit multi-core resources with the same source code.

关键词： AES PRNG heterogeneous programming Multi-cores GPUs

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Assessing and discovering parallelism in C plus plus code for heterogeneous platforms

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JOURNAL OF SUPERCOMPUTING 2018年第11期74卷 5674-5689页

作者： del Rio Astorga, David Sotomayor, Rafael Miguel Sanchez, Luis Garcia Blas, Javier Calderon, Alejandro Fernandez, Javier Univ Carlos III Avda Univ 30 Madrid 28911 Spain

Massively parallel architectures are mainly based on a parallel heterogeneous setup. They are composed by different computing devices that speed up specific code regions, named kernels. These kernels are usually executed offline in the corresponding devices. Porting applications to a specific heterogeneous platform is a costly task in terms of time and human resources. The key points in the porting process are the manual analysis of the source code and kernel detection. Each device of these heterogeneous platforms has their own restrictions, such as the memory allocation support. Kernels must be mapped with suitable computing devices. We introduced AKI as an automatic kernel identification and annotation tool that aims to identify potential kernels on C sequential applications. AKI identifies those kernels that can be offlined on heterogeneous computing devices. To annotate these kernels, REPARA C++ attributes have been defined. This annotation mechanism can aid future automatic source-to-source transformation tools to facilitate the work for parallel heterogeneous platforms. AKI has been evaluated over all benchmarks included in the NAS suite. The benchmark suite incorporates a big set of realistic high performance applications. The evaluation results demonstrate that AKI is a competitive solution for identifying and annotating parallel code fragments (aka kernels).

关键词： heterogeneous programming Parallelism discovery Parallel programming

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Efficient fine-grained shared buffer management for multiple OpenCL devices

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Journal of Zhejiang University-Science C(Computers and Electronics) 2013年第11期14卷 859-872页

作者： Chang-qing XUN Dong CHEN Qiang LAN Chun-yuan ZHANG College of Computer National University of Defense Technology State Key Laboratory of High Performance Computing National University of Defense Technology

OpenCL programming provides full code portability between different hardware platforms,and can serve as a good programming candidate for heterogeneous systems,which typically consist of a host processor and several ***,to make full use of the computing capacity of such a system,programmers are requested to manage diverse OpenCL-enabled devices explicitly,including distributing the workload between different devices and managing data transfer between multiple *** these tedious jobs pose a huge challenge for *** this paper,a distributed shared OpenCL memory(DSOM) is presented,which relieves users of having to manage data transfer explicitly,by supporting shared buffers across *** allocates shared buffers in the system memory and treats the on-device memory as a software managed virtual cache *** support fine-grained shared buffer management,we designed a kernel parser in DSOM for buffer access range analysis.A basic modified,shared,invalid cache coherency is implemented for DSOM to maintain coherency for cache *** addition,we propose a novel strategy to minimize communication cost between devices by launching each necessary data transfer as early as *** strategy enables overlap of data transfer with kernel *** experimental results show that the applicability of our method for buffer access range analysis is good,and the efficiency of DSOM is high.

关键词： Shared buffer OpenCL heterogeneous programming Fine grained

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