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ACM Workshop on Software Engineering Methods for Parallel and High Performance Applications (SEM4HPC)

作者： Li, Shuo Intel Corp 2111 NE 25th Ave Hillsboro OR 97124 USA

ISBN: (纸本)9781450343510

heterogeneous computing platforms with multicore host system and many-core accelerator devices have taken a major step forward in the mainstream HPC computing market this year with the announcement of HP Apollo 6000 System's ProLiant XL250a server features the Intel (R) Xeon Phi (TM) coprocessors. Although many application developers attempt to use it in the same way as GPGPU acceleration platforms, doing so forfeits the processing capability of multicore host processors and introduces power inefficiency in business operations. In this paper, we propose an application optimization framework to turn sequential legacy applications into highly parallel applications that make use of the hardware resources both on the host CPU and on the accelerator devices to enable simultaneous heterogeneous computing. As a case study, we look at how to apply this framework and adopt a structured methodology to develop option pricing applications to take advantages of a heterogeneous computing environment.

关键词： programming Model Performance Measurement Many-core programming vector programming Development Tools application acceleration Power consumption multithreaded parallelism heterogeneous programming

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Native Offload of Haskell Repa Programs to Integrated GPUs 3

Native Offload of Haskell Repa Programs to Integrated GPUs

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3rd ACM SIGPLAN Workshop on Functional High-Performance Computing (FHPC)

作者： Liu, Hai Day, Laurence E. Glew, Neal Anderson, Todd A. Barik, Rajkishore Intel Labs Santa Clara CA 95054 USA

ISBN: (纸本)9781450330404

In light of recent hardware advances, general-purpose computing on graphics processing units (GPGPU) is becoming increasingly commonplace, and needs novel programming models due to GPUs' radically different architecture. For the most part, existing approaches to programming GPUs within a high-level programming language choose to embed a domain-specific language (DSL) within a host metalanguage and then implement a compiler that maps programs written within that DSL to code in low-level languages such as OpenCL or CUDA. An alternative, underexplored, approach is to compile a restricted subset of the host language itself directly down to OpenCL/CUDA. We believe more research should be done to compare these two approaches and their relative merits. As a step in this direction, we implemented a quick proof of concept of the alternative approach. Specifically, we extend the Repa library with a computeG function to offload a computation to the GPU. As long as the requested computation meets certain restrictions, we compile it to OpenCL 2.0 using the recently added feature for shared virtual memory. We can successfully run nine benchmarks on an Intel integrated GPU. We obtain the expected performance from the GPU on six of those benchmarks, and are close to the expected performance on two more. In this paper, we describe an offload primitive for Haskell, how to extend Repa to use it, how to implement that primitive in the Intel Labs Haskell Research Compiler, and evaluate the approach on nine benchmarks, comparing to two different CPUs, and for one benchmark to handwritten OpenCL code.

关键词： GPU programming heterogeneous programming Haskell

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How to deploy AI software to self driving cars 19

How to deploy AI software to self driving cars

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8th International Workshop on OpenCL (IWOCL)

作者： Brown, Gordon Ravindran, Meenakshi Burns, Rod Miller, Nicolas

ISBN: (纸本)9781450362306

The automotive industry is embracing new challenges to deliver self-driving cars, and this in turn requires increasingly complex hardware and software. Software developers are leveraging artificial intelligence, and in particular machine learning, to deliver the capabilities required for an autonomous vehicle to operate. This has driven automotive systems to become increasingly heterogeneous offering multi-core processors and custom co-processors capable of performing the intense algorithms required for artificial intelligence and machine learning. These new processors can be used to vastly speed up common operations used in AI (Artificial Intelligence) and machine learning *** R-Car V3H system-on-chip (SoC) from the Renesas AutonomyâĎć platform for ADAS (Advanced Driver Assistance Systems) and automated driving supports Level 3 and above (as defined by SAE's automation level definitions). It follows the heterogeneous IP concept of the Renesas Autonomy platformâĎć, giving the developer the choice of high performance computer vision at low power consumption, as well as flexibility to implement the latest algorithms such as those used in machine *** examining the architecture of the R-Car hardware we can understand how this differs from HPC and desktop heterogeneous systems, and how this can be mapped to the SYCL and OpenCL programming models. When both power consumption and performance are important, as is the case in the automotive industry, the focus for implementing OpenCL and SYCL on these hardware platforms must be a balanced approach. The memory capacity and layout must be used in the most optimum way to build a pipeline that provides the best throughput. The R-Car hardware provides DMA and on-chip memory where these are used to facilitate efficient data transfer on the device. The memory hierarchy layers can be seen on how it is efficiently mapped to OpenCL *** R-Car hardware also offers many fixed function IP blocks, each performin

关键词： C plus OpenCL SYCL parallelism concurrency heterogeneous programming distributed programming models

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Experiences Building an MLIR-Based SYCL Compiler 24

Experiences Building an MLIR-Based SYCL Compiler

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22nd IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

作者： Tiotto, Ettore Perez, Victor Tsang, Whitney Sommer, Lukas Oppermann, Julian Lomueller, Victor Goli, Mehdi Brodman, James Intel Corp Toronto ON Canada Codeplay Software Edinburgh Midlothian Scotland Intel Corp Boston MA USA

ISBN: (纸本)9798350395099

Similar to other programming models, compilers for SYCL, the open programming model for heterogeneous computing based on C++, would benefit from access to higher-level intermediate representations. The loss of high-level structure and semantics caused by premature lowering to low-level intermediate representations and the inability to reason about host and device code simultaneously present major challenges for SYCL compilers. The MLIR compiler framework, through its dialect mechanism, allows to model domain-specific, high-level intermediate representations and provides the necessary facilities to address these challenges. This work therefore describes practical experience with the design and implementation of an MLIR-based SYCL compiler. By modeling key elements of the SYCL programming model in host and device code in the MLIR dialect framework, the presented approach enables the implementation of powerful device code optimizations as well as analyses across host and device code. Compared to two LLVM-based SYCL implementations, this yields speedups of up to 4.3x on a collection of SYCL benchmark applications. Finally, this work also discusses challenges encountered in the design and implementation and how these could be addressed in the future.

关键词： SYCL MLIR compiler optimization heterogeneous programming

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Approach for Accelerating Image Enhancement Processes: Optimized OpenCL Architecture 4

Approach for Accelerating Image Enhancement Processes: Optim...

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4th International Symposium on Multidisciplinary Studies and Innovative Technologies, ISMSIT 2020

作者： Aslan, Menduh Furkan Goksu, Tuna Antalya Bilim Üniversitesi Elektrik-Elektronik Mühendisliǧi Bölümü Antalya Turkey Isparta Uygulamalı Bilimler Üniversitesi Elektrik-Elektronik Mühendisliǧi Bölümü Antalya Turkey

ISBN: (纸本)9781728190907

Computer technology, which continues to develop today, often has difficulties in meeting the needs of signal and image processing software. As a result of the developing technology, software needs larger memory and faster processor. Parallel programming method has been developed to solve the speed problems of processors. In this study, OpenCL based image enhancement applications that can work in parallel on the graphics processor unit have been implemented.. The OpenCL architecture has been optimized to maximize the amount of acceleration. Appropriate image enhancement applications have been tested to observe that the designed algorithm and architecture are successful in simple or complex operations. In order to make sense of the speed gain, the same applications were developed with serial programming technique and the results obtained were compared with the applications developed in parallel. It is supported by the comparison results that parallel programming is better in terms of performance. Due to the parallel programming for the hardware used, it was observed that the calculation times were reduced by 1.58 times to 561 times. © 2020 IEEE.

关键词： heterogeneous programming OpenCL Parallel programming Performance Analysis

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SDSoC: A Higher-level programming Environment for Zynq SoC and Ultrascale plus MPSoC 16

SDSoC: A Higher-level Programming Environment for Zynq SoC a...

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ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)

作者： Kathail, Vinod Hwang, James Sun, Welson Chobe, Yogesh Shui, Tom Carrillo, Jorge Xilinx 2100 Log Dr San Jose CA 95124 USA

ISBN: (纸本)9781450338561

Zynq-7000 All Programmable SoC and the new Zynq Ultrascale+ MPSoC provide proven alternatives to traditional domain-specific application SoCs and enable extensive system-level differentiation, integration and flexibility through hardware, software and I/O programmability. The SDSoC Development Environment is a heterogeneous design environment for implementing embedded systems using the Zynq SoC and MPSoC. It enables the broader community of embedded software developers to leverage the power of hardware and software programmable devices, entirely from a higher-level of abstraction. The SDSoC environment provides a greatly simplified embedded C/C++ application programming experience including an easy-to-use Eclipse IDE and a comprehensive development platform. SDSoC includes a full-system optimizing C/C++ compiler, system-level profiling and hardware/software event tracing, automated software acceleration in programming logic, automated generation of SW-HW connectivity, and integration with libraries to speed programing. The SDSoC compiler transforms programs into complete hardware/software systems based on user-specified target platform and functions within the program to compile into programmable hardware logic. Hardware accelerators communicate with the CPU and external memory through an automatically-generated, application-specific data motion network comprised of DMAs, interconnects and other standard IP blocks. The SDSoC Environment also provides flows for customer and 3rd party developers to enable their platforms and integrate RTL IPs as C-callable libraries. It builds upon customer-proven design tools from Xilinx including Vivado Design Suite, Vivado High-level Synthesis and SDK. In this presentation, we will introduce the motivation and basic concepts behind SDSoC, describe its capabilities and the user-flow, and provide a brief demonstration of the tool using an example.

关键词： sdsoc sw-hw connectivity higher-level programming for cpu and fpga systems software-defined systems-on-chip zynq and zynq ultrascale+ mpsoc programming environment heterogeneous architecture exploration heterogeneous programming sw-hw design exploration high-level synthesis

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CLOP: A Multi-stage Compiler to Seamlessly Embed heterogeneous Code

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ACM SIGPLAN NOTICES 2016年第3期51卷 109-112页

作者： Makarov, Dmitri Hauswirth, Matthias Univ Svizzera Italiana Lugano Switzerland

heterogeneous programming complicates software development. We present CLOP, a platform that embeds code targeting heterogeneous compute devices in a convenient and clean way, allowing unobstructed data flow between the host code and the devices, reducing the amount of source code by an order of magnitude. The CLOP compiler uses the standard facilities of the D programming language to generate code strictly at compile-time. In this paper we describe the CLOP language and the CLOP compiler implementation.

关键词： Languages Generative programming heterogeneous programming Embedded Languages Staging

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Overhauling SC Atomics in C11 and OpenCL

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ACM SIGPLAN NOTICES 2016年第1期51卷 634-648页

作者： Batty, Mark Donaldson, Alastair F. Wickerson, John Univ Kent Canterbury CT2 7NZ Kent England Univ London Imperial Coll Sci Technol & Med London SW7 2AZ England

Despite the conceptual simplicity of sequential consistency (SC), the semantics of SC atomic operations and fences in the C11 and OpenCL memory models is subtle, leading to convoluted prose descriptions that translate to complex axiomatic formalisations. We conduct an overhaul of SC atomics in C11, reducing the associated axioms in both number and complexity. A consequence of our simplification is that the SC operations in an execution no longer need to be totally ordered. This relaxation enables, for the first time, efficient and exhaustive simulation of litmus tests that use SC atomics. We extend our improved C11 model to obtain the first rigorous memory model formalisation for OpenCL (which extends C11 with support for heterogeneous many-core programming) In the OpenCL setting, we refine the SC axioms still further to give a sensible semantics to SC operations that employ a 'memory scope' to restrict their visibility to specific threads. Our overhaul requires slight strengthenings of both the C11 and the OpenCL memory models, causing some behaviours to become disallowed. We argue that these strengthenings are natural, and that all of the formalised C11 and OpenCL compilation schemes of which we are aware (Power and x86 CPUs for C11, AMD GPUs for OpenCL) remain valid in our revised models. Using the HERD memory model simulator, we show that our overhaul leads to an exponential improvement in simulation time for C11 litmus tests compared with the original model, making exhaustive simulation competitive, time-wise, with the non-exhaustive CDSChecker tool.

关键词： Formal methods graphics processing unit (GPU) heterogeneous programming HOL theorem prover language design program simulation weak memory models

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High performance heterogeneous embedded computing: a review

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Instrumentation 2014年第2期1卷 1-12页

作者： HE Yongfu WANG Shaojun PENG Yu Department of Automatic Test and Control Harbin Institute of TechnologyHarbin 150080China

As increasingly widening gap of computing demand and performance in embedded computing domain,heterogeneous computing architecture which delivers better performance as well as lower power in limited size is gaining more and more attention. At first,the heterogeneous computing model is presented. And the different tightly coupled single chip heterogeneous architectures and their application domain are introduced. Then,task partitioning methods are described. Several programming model technology are analyzed and discussed. Finally,main challenges and future perspective of High Performance Embedded Computing(HPEC) are summarized.

关键词： HPEC heterogeneous SoCs hardw are/softw are partition heterogeneous programming

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Parallel QR Factorization using Givens Rotations in MPI-CUDA for Multi-GPU

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INTERNATIONAL JOURNAL OF ADVANCED COMPUTER SCIENCE AND APPLICATIONS 2020年第5期11卷 636-645页

作者： Tapia-Romero, Miguel Meneses-Viveros, Amilcar Hernandez-Rubio, Erika IPN CINVESTAV Dept Comp Mexico City DF Mexico Inst Politecn Nacl SEPI ESCOM Mexico City DF Mexico

Modern supercomputers incorporate the use of multi-core processors and graphics processing units. Applications running on these computers take advantage of these technologies with scalable programs that work with multicores and accelerator such as graphics processing unit. QR factorization is essential for several numerical tasks, such as linear equations solvers, compute inverse matrix or compute a diagonal matrix, to name a few. There are several factorization algorithm such as LU, Cholesky, Givens and Householder, among others. The efficient parallel implementation of each parallelization algorithm will depend on the structure of the data and the type of parallel architecture used. A common strategy in parallel programming is to break a problem into subproblems to solve them in different processing units. This is very useful when dealing with complex problems or when the data is too large to work with the available memory. However, it is not clear how data partitioning affects subtask performance when mapping to processing units, specifically to graphical processing units. This work explores the partitioning of large symmetric matrix data for QR factorization using Givens rotations and its parallel implementation using MPI and CUDA is presented.

关键词： Givens factorization CUDA heterogeneous programming scalable parallelism

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