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29th International Conference on Real-Time Networks and Systems (RTNS)

作者： Mascitti, Agostino Cucinotta, Tommaso Scuola Super Sant Anna Pisa Italy

ISBN: (纸本)9781450390019

This paper evaluates the combination of a Directed Acyclic Graph (DAG) task splitting technique already proposed in the literature and the state-of-the-art, energy-aware version of the well-known CBS server (BL-CBS), which dynamically partitions and schedules real-time task sets in an energy-efficient way on multi-core platforms based on the ARM *** architecture. The approach is designed to be used with any DAG in a transparent way as an on-line and adaptive scheduler supporting "open" systems. The approach is validated and evaluated through the open-source RTSim simulator, which has been extended integrating an energy model of the ODROID-XU3 board and the code-base needed to perform the DAG task decomposition and scheduling. Simulations on randomly generated DAGs show that the approach leads to promising results.

关键词： Real-time scheduling ARM big.LITTLE heterogeneous multicore processing energy-efficiency DAG scheduling

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Combining admission tests for heuristic partitioning of real-time tasks on ARM *** multi-processor architectures

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JOURNAL OF SYSTEMS ARCHITECTURE 2021年 119卷 102229-102229页

作者： Mascitti, Agostino Cucinotta, Tommaso Abeni, Luca Scuola Super Sant Anna Via Moruzzi 1 I-56124 Pisa Italy

This paper tackles the problem of admitting real-time tasks on non-symmetric multiprocessor platforms, where partitioned EDF-FF is used. We extend the already obtained results for symmetric multiprocessor platforms and provide an improved equation based on the number of tasks in the taskset that considers the first few heaviest tasks in the taskset. This equation has been enveloped in three effective and efficient admission tests that are suitable for being used online and in dynamic environments to partition and admit tasks on NUMP platforms and, specifically, on ARM *** architectures. This results in an improvement of the state of the art in terms of the considered architectures and looks promising in terms of admitted tasksets as shown by an extensive number of tests performed on tasksets generated randomly with the widely adopted randfixedsum algorithm.

关键词： Real-time scheduling ARM big.LITTLE heterogeneous multicore processing EDF admission test

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Dynamic partitioned scheduling of real-time tasks on ARM *** architectures

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JOURNAL OF SYSTEMS AND SOFTWARE 2021年 173卷 110886-110886页

作者： Mascitti, Agostino Cucinotta, Tommaso Marinoni, Mauro Abeni, Luca Scuola Super Sant Anna Via Moruzzi 1 I-56124 Pisa Italy

This paper presents Big-LITTLE Constant Bandwidth Server (BL-CBS), a dynamic partitioning approach to schedule real-time task sets in an energy-efficient way on multi-core platforms based on the ARM *** architecture. BL-CBS is designed as an on-line and adaptive scheduler, based on a push/pull architecture that is suitable to be incorporated in the current SCHED_DEADLINE code base in the Linux kernel. It employs a greedy heuristic to dynamically partition the real-time tasks among the big and LITTLE cores aiming to minimize the energy consumption and the migrations imposed on the running tasks. The new approach is validated through the open-source RT-Sim simulator, which has been extended integrating an energy model of the ODROID-XU3 board, fitting tightly the power consumption profiles for the big and LITTLE cores of the board. An extensive set of simulations have been run with randomly generated real-time task sets, leading to promising results. (C) 2020 Elsevier Inc. All rights reserved.

关键词： Real-time scheduling ARM big LITTLE heterogeneous multicore processing Energy-efficiency

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DSP IN heterogeneous multicore EMBEDDED SYSTEMS - A LABORATORY EXPERIMENT 22

DSP IN HETEROGENEOUS MULTICORE EMBEDDED SYSTEMS - A LABORATO...

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22nd European Signal processing Conference (EUSIPCO)

作者： Lifshits, Pavel Eilam, Alon Moshe, Yair Peleg, Nimrod Technion Israel Inst Technol Dept Elect Engn SIPL IL-32000 Haifa Israel

ISBN: (纸本)9780992862619

Undergraduate engineering students who are learning Digital Signal processing (DSP) are expected to have the ability to implement their theoretical knowledge in various applications soon after graduation. In this paper, we present a laboratory experiment developed for undergraduate students that addresses the challenge of getting them familiar with implementing DSP algorithms in heterogeneous multicore systems. In a top-down approach, the students first gain control of the development environment, and then implement DSP algorithms on a general purpose and on a digital signal processor core. Through the experiment, they get to appreciate the advantages of DSP core architecture in performing signal processing algorithms, and learn methods for timing and data transfer between cores while meeting real-time constraints. In a limited time frame, this hands-on laboratory experiment exposes the students to state-of-the-art multicore development practices and increases their knowledge and interest in DSP and in embedded programming.

关键词： Electrical engineering education heterogeneous multicore processing digital signal processing fixed-point arithmetic BeagleBoard

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DSP IN heterogeneous multicore EMBEDDED SYSTEMS-A LABORATORY EXPERIMENT

DSP IN HETEROGENEOUS MULTICORE EMBEDDED SYSTEMS-A LABORATORY...

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European Signal processing Conference

作者： Pavel Lifshits Alon Eilam Yair Moshe Nimrod Peleg Signal and Image Processing Laboratory (SIPL) Department of Electrical Engineering Technion - Israel Institute of Technology

ISBN: (纸本)9781479946037

关键词： Electrical engineering education heterogeneous multicore processing Digital signal processing Fixed-point arithmetic BeagleBoard

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