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A Fully Parallel LDPC decoder Architecture Using Probabilistic Min-Sum Algorithm for high-throughput Applications

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2014年第9期61卷 2738-2746页

作者： Cheng, Chung-Chao Yang, Jeng-Da Lee, Huang-Chang Yang, Chia-Hsiang Ueng, Yeong-Luh Natl Tsing Hua Univ Dept Elect Engn Hsinchu Taiwan Natl Chiao Tung Univ Dept Elect Engn Hsinchu Taiwan Natl Tsing Hua Univ Inst Commun Engn Hsinchu Taiwan

This paper presents a normalized probabilistic min-sum algorithm for low-density parity-check (LDPC) codes, where a probabilistic second minimum value, instead of the true second minimum value, is used to facilitate fully parallel decoder realization. The comparators in each check-node unit (CNU) are connected through an interconnect network based on a mix of tree and butterfly networks such that the routing and message passing between the variable-node units (VNUs) and CNUs can be efficiently realized. In order to further reduce the hardware complexity, the normalization operation is realized in the VNU rather than in the CNU. An early termination scheme is proposed in order to prevent unnecessary energy dissipation for both low and high signal-to-noise-ratio regions. The proposed techniques are demonstrated by implementing a (2048, 1723) LDPC decoder using a 90 nm CMOS process. Post-layout simulation results show that the decoder supports a throughput of 45.42 Gbps at 199.6 MHz, achieving the highest throughput and throughput-to-area ratio among comparable works based on a similar or better error performance.

关键词： high-throughput decoder low-density parity-check (LDPC) codes min-sum algorithm

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Latency-Optimized Stochastic LDPC decoder for high-throughput Applications

Latency-Optimized Stochastic LDPC Decoder for High-Throughpu...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Wu, Di Chen, Yun Zhang, Qichen Zheng, Lirong Zeng, Xiaoyang Ueng, Yeong-luh Fudan Univ State Key Lab ASIC & Syst Shanghai 200433 Peoples R China Natl Tsing Hua Univ Dept Elect Engn Hsinchu 30013 Taiwan

ISBN: (纸本)9781479983919

Stochastic decoding can be applied to Low-Density Parity-Check codes in order to achieve high throughput with less area. However, most architectures suffer from large decoding latencies, due to the mechanism of stochastic computation. In this paper, three novel strategies, including the LUT-based initialization, the posterior-information-based hard decision and the Bit-Flipping-based post processing, are proposed in order to reduce decoding latency and hence improve throughput. For the standard IEEE 802.3an (2048, 1723) code, simulation indicates 75.7% reduction in average decoding cycles at 4.5 dB with satisfied bit error rate. Moreover, hardware implementation shows that the area of variable node units is reduced significantly in SMIC 65 nm technology.

关键词： Bit-Flipping Algorithm Low-Density Parity-Check Codes high-throughput decoder Stochastic decoding

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Latency-Optimized Stochastic LDPC decoder for high-throughput Applications

Latency-Optimized Stochastic LDPC Decoder for High-Throughpu...

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IEEE International Symposium on Circuits and Systems

作者： Di Wu Yun Chen Qichen Zhang Lirong Zheng Xiaoyang Zeng Yeong-luh Ueng State Key Laboratory of ASIC & system Fudan University Shanghai China Department of Electrical Engineering National Tsing Hua University Taiwan

ISBN: (纸本)9781479983926

关键词： Bit-Flipping Algorithm Low-Density Parity-Check Codes high-throughput decoder Stochastic decoding

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An Efficient high-Rate Non-Binary LDPC decoder Architecture With Early Termination

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IEEE ACCESS 2019年 7卷 20302-20315页

作者： Li, Mao-Ruei Chu, Wei-Xiang Lee, Huang-Chang Ueng, Yeong-Luh Natl Tsing Hua Univ Dept Elect Engn Hsinchu 30013 Taiwan Chang Gung Univ Dept Elect Engn Taoyuan 33302 Taiwan Natl Tsing Hua Univ Inst Commun Engn Dept Elect Engn Hsinchu 30013 Taiwan

This paper presents a modified Trellis Min-Max (T-MM) algorithm together with the associated architecture for non-binary (NB) low-density parity-check (LDPC) decoders. The proposed T-MM algorithm is able to reduce the memory requirements for the check-node messages through an efficient compression method and enhance the error-rate performance using the appropriate decompression. A method of updating the a posteriori log-likelihood ratio in the delta domain is used to simplify the computational and storage complexity. In order to enhance the decoding throughput, a low-complexity early termination (ET) scheme is devised by using the hard decisions of the variable-to-check messages, where, although a minor overhead is introduced, there is no visible degradation in error rate. As a proof of concept, a row-parallel layered decoder for the 32-ary (837, 726) LDPC code is implemented using a 90-nm CMOS process. The proposed decoder achieves a throughput of 1.64 Gb/s at 526.32 MHz based on eight iterations and has an area of 6.86 mm(2). When the ET scheme is enabled, the decoder achieves a maximum throughput of 4.68 Gb/s with a frame error rate of 3.25 x 10(-6) at E-b/N-0 = 4.5 dB. The proposed NB-LDPC decoder achieves the highest throughput and hardware efficiency compared to the state-of-the-art decoders, even when the ET scheme is not enabled.

关键词： Non-binary low-density parity-check (NB-LDPC) codes trellis min-max (T-MM) algorithm layered decoding early termination (ET) high-throughput decoder very large scale integration (VLSI) architecture

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A 124-Gb/s decoder for Generalized Integrated Interleaved Codes

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2019年第8期66卷 3174-3187页

作者： Li, Wenjie Lin, Jun Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Jiangsu Peoples R China

Generalized integrated interleaved (GII) codes have attracted much attention in distributed storage systems since they can reduce the overall redundancy by creating redundancy shared by the interleaves. The Berlekamp-Massey (BM) algorithm makes the GII decoding efficient by reusing the preceding results at each decoding stage. However, it also forms the speed bottleneck of GII decoders. The reformulated inversionless Berlekamp-Massey (riBM) algorithm is well known for its short critical path, but it is not generally suitable for GII decoding since its polynomials are difficult to be reused directly. In this paper, we address this issue by reinitializing the polynomials and propose a riBM-based GII decoding algorithm. In our simulations, slight performance degradation induced by the first-layer miscorrection is observed in the high signal-to-noise ratio (SNR) region. Hence, a subtle method is introduced to handle the miscorrected interleaves. Furthermore, the hardware architecture of the proposed decoding algorithm is developed and a high throughput decoder for the given example GII code is implemented. The synthesis results under TSMC 28-nm technology show that the decoder can achieve a throughput of up to 124 Gb/s. Moreover, the decoder has been implemented into a field-programmable gate array (FPGA) to validate its error-correction performance.

关键词： Generalized integrated interleaved (GII) codes Reed-Solomon (RS) codes hardware implementation high-throughput decoder reformulated inversionless Berlekamp-Massey (riBM) algorithm

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A New Probabilistic Gradient Descent Bit Flipping decoder for LDPC Codes

A New Probabilistic Gradient Descent Bit Flipping Decoder fo...

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IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Cui, Hangxuan Lin, Jun Song, Suwen Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing Jiangsu Peoples R China

ISBN: (纸本)9781728103976

Probabilistic gradient descent bit-flipping (PGDBF) is the state-of-the-art hard-decision algorithm for decoding low-density parity-check (LDPC) codes on binary symmetric channel (BSC). However, there still exists a considerable performance gap between the PGDBF algorithm and soft-decision algorithms, especially in the error-floor region. To bridge this performance gap, a tabu-list aided PGDBF (T-PGDBF) algorithm is proposed in this paper. In the T-PGDBF algorithm, a tabu-list is employed to help the decoding escape from trapping sets, which is the main cause of the error-floor phenomenon. The bits which are flipped in the current iteration will be added to the tabu-list to prevent them being flipped in the next iteration. Simulation results show that the T-PGDBF algorithm offers a significant performance gain when compared to the PGDBF algorithm, which can reach that of soft-decision algorithms. We also present the hardware architecture to implement the T-PGDBF algorithm. Synthesis results show that the improved performance offered by the T-PGDBF algorithm can be obtained with a small hardware overhead.

关键词： Probabilistic gradient descent bit-flipping low-density parity-check codes tabu-list trapping sets high-throughput decoder

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Strategies for Reducing Decoding Cycles in Stochastic LDPC decoders

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2016年第9期63卷 873-877页

作者： Wu, Di Chen, Yun Zhang, Qichen Ueng, Yeong-luh Zeng, Xiaoyang Fudan Univ State Key Lab Applicat Specif Integrated Circuit Shanghai 200433 Peoples R China Natl Tsing Hua Univ Dept Elect Engn Hsinchu 30013 Taiwan Natl Tsing Hua Univ Inst Commun Engn Hsinchu 30013 Taiwan

This brief presents three strategies, including initialization based on Look Up Table (LUT), postprocessing based on bit flipping and hard decision based on the posterior information, to reduce the number of decoding cycles (DCs) for stochastic low-density parity-check decoding. For the standard IEEE 802.3an code, simulation indicates a 73.6% reduction in the average number of DCs with a satisfactory bit error rate. Moreover, hardware implementation shows that the area required for the proposed decoder is significantly reduced.

关键词： Bit-flipping algorithm high-throughput decoder low-density parity-check (LDPC) codes stochastic decoding

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A Low-Complexity Dual Trellis Decoding Algorithm for high-Rate Convolutional Codes

A Low-Complexity Dual Trellis Decoding Algorithm for High-Ra...

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IEEE Wireless Communications and Networking Conference (IEEE WCNC)

作者： Vinh Hoang Son Le Nour, Charbel Abdel Douillard, Catherine Boutillon, Emmanuel IMT Atlantique Lab STICC UMR CNRS 6285 F-29238 Brest France Univ Bretagne Sud Lab STICC UMR CNRS 6285 F-56321 Lorient France

ISBN: (纸本)9781728131061

Decoding using the dual trellis is considered as a potential technique to increase the throughput of soft-input soft-output decoders for high coding rate convolutional codes. However, the dual Log-MAP algorithm suffers from a high decoding complexity. More specifically, the source of complexity comes from the soft-output unit, which has to handle a high number of extrinsic values in parallel. In this paper, we present a new low-complexity sub-optimal decoding algorithm using the dual trellis, namely the dual Max-Log-MAP algorithm, suited for high coding rate convolutional codes. A complexity analysis and simulation results are provided to compare the dual Max-Log-MAP and the dual Log-MAP algorithms. Despite a minor loss of about 0.2 dB in performance, the dual Max-Log-MAP algorithm significantly reduces the decoder complexity and makes it a first-choice algorithm for high-throughput high-rate decoding of convolutional and turbo codes.

关键词： Convolutional codes high coding rate dual trellis high-throughput decoder low-complexity decoder turbo codes

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