In pyramidal wavelet representation, an image is decomposed into multiresolution and multifrequency subbands with sets of tree-structured coefficients, Le. a spatial orientation tree which consists of coefficients at ...
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In pyramidal wavelet representation, an image is decomposed into multiresolution and multifrequency subbands with sets of tree-structured coefficients, Le. a spatial orientation tree which consists of coefficients at different resolutions and different orientations but associated with the same spatial location. The magnitudes of the coefficients in these trees measure the signal activity level of the corresponding spatial areas. A novel coefficient partitioning algorithm is introduced for splitting the coefficients into two sets using a spatial orientation tree data structure. By splitting the coefficients, the overall theoretical entropy is reduced due to the different probability distributions for the two coefficient sets. In the spatial domain, it is equivalent to identifying smooth regions of the image. A lossless coder based on this spatial coefficient partitioning has a better coding performance than other wavelet-based lossless image coders such as S + P and JPEG-2000.
This paper proposes a simple low memory architecture for computing discrete wavelet transform (DWT) of high-resolution (HR) images on low-cost memory-constrained sensor nodes used in visual sensor networks (VSN) or In...
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This paper proposes a simple low memory architecture for computing discrete wavelet transform (DWT) of high-resolution (HR) images on low-cost memory-constrained sensor nodes used in visual sensor networks (VSN) or Internet of Multimedia Things (IoMT). The main feature of the proposed architecture is the novel data scanning technique that makes memory requirement independent of the image size. The proposed architecture needs only (30S) words of memory, where S is the number of parallel processing units and a critical path delay (CPD) equal to the delay of a multiplier (T-m). Furthermore, a multiplierless version of this architecture is also proposed which reduces the CPD to T-aimage of dimension 2048 x 2048. Moreover, the proposed architecture needs no LUTRAM and DSP, whereas the existing architecture requires 3264 LUTRAM and 24 DSP's. Thus the proposed multiplierless architecture is superior to the existing state-of-the-art architecture and is suitable for IoMT/VSNs.
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