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36th International Conference on VLSI Design (VLSID) / 22nd International Conference on Embedded Systems (ES)

作者： Prasad, Kailash Srivastava, Ayush Baruah, Nistha Mekie, Joycee Indian Inst Technol Gandhinagar Gandhinagar Gujarat India Natl Inst Technol Silchar Cachar Assam India

ISBN: (纸本)9798350346787

Digital In-memory computing (IMC) in SRAM promises a robust and energy-efficient solution to the Von Neumann bottleneck. This paper comprehensively analyzes the challenges associated with the technology scaling aspects of Sense Amplifier design for digital IMC. We show that the existing Sense Amplifier (SA) designs fail due to process variations at lower technology nodes resulting in incorrect compute outputs. Using our analysis, we show how the existing SA designs can be modified to obtain error-free output but with additional design constraints. We propose a novel area-efficient zero-error Compute-Enabled Sense Amplifier (CESA). We perform a detailed analysis of CESA, for which we have implemented 128 x 128 SRAM IMC array along with all the peripherals and compute logic in CMOS 28nm and show the CESA works correctly under process variations. The proposed CESA improves the compute access time and energy by 20.4% and 5.95%, respectively, and read access time and energy by 16.67% and 55.87%, respectively. The SRAM IMC with CESA and Compute circuit works at 1.43 GHz and has 56 TOPS/W/bit energy efficiency for the addition operation. Finally, we model the SA errors for neural networks and find that in LENET-5 NN, the accuracy degrades to similar to 12% for SA with error, whereas the proposed error-free SA maintains the accuracy to its baseline value of 98.5%.

关键词： SRAM in memory computing Sense Amplifier

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Enabling Energy-Efficient In-memory computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array

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IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 2023年第1期13卷 445-455页

作者： Soundrapandiyan, Kavitha Vishvakarma, Santosh Kumar Reniwal, Bhupendra Singh IIITDM Kancheepuram Dept Elect & Commun Chennai 600127 India Indian Inst Technol Indore Dept Elect Engn Indore 453552 Madhya Pradesh India Indian Inst Technol IIT Jodhpur Dept Elect Engn Jodhpur 342030 Rajasthan India

With the increasing gap between processing speed and memory bandwidth necessity for in/near-memory computing has emerged, to ensure high-performance, energy-efficient computing for data-intensive applications at the edge. This work proposes a feasible SRAM compute cache with a sense amplifier (SA) based approach to perform in-/near memory Boolean computations with a novel reconfigurable assist sense amplifier (RASA). The RASA exploits assist transistors to achieve NAND, NOR and XNOR operations without affecting the transparency of normal read leading to fast and reliable sensing with only one SA. This effectively eliminates the need for two SAs in comparison to state-of-the-art solutions. The proposed work improves memory density and reduces cost-per-bit by leveraging the SA-based approach because existing solutions lead to significant area overhead/cell which reflects overhead multiply by the number of cells/column. The RASA provides flexibility to accommodate more cells per column at the architecture level. Extensive Monte-Carlo analysis is performed to verify the feasibility of the proposed circuit in commercial 65nm UMC technology under iso-SA area and iso-yield conditions. Simulations indicate a 34.34%, 84.87%, 81.21%, 75.46% improvement in energy, and a 71.30%, 43.36%, 32.49%, 17.44% improvement in throughput leading to a reduction of 60.97%, 91.37%, 87.22%, 79.62% in energy-delay product with respect to CLSA (Dong et al., 2018), CSRAM (Chen et al., 2021), RRCSA (Rajput et al., 2022) and the ADSA (Agrawal et al., 2018) respectively. An improvement in the area of SA by 36.512% is achieved with respect to RRCSA.

关键词： Random access memory Computer architecture In-memory computing Decoding Bandwidth Arithmetic Transistors Assist device sense amplifier in memory computing digital Boolean logic

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CMOS Pipelined in-memory computing Circuit for Column-Wise Image Sensor Architectures 31

CMOS Pipelined in-Memory Computing Circuit for Column-Wise I...

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31st Conference on Electronics Circuits and Systems

作者： Domenech-Asensi, Gines Andreo-Oliver, Francisco Javier Diaz-Madrid, Jose Angel Ruiz-Merino, Ramon Univ Politecn Cartagena Dept Elect Tec Comp & Proyectos Cartagena Spain Ctr Univ Def UPCT Dept Ingn & Tecn Aplicadas Cartagena Spain

ISBN: (纸本)9798350377217;9798350377200

This paper presents a CMOS binary neural network architecture specifically aimed to perform inferences on CMOS image sensors. The circuits is based on a pipelined structure which exploits the column-wise structure of most CMOS image sensors to process successive image rows at the same rate they are read from the sensor. This allows a reduction of the memory required to store the activations of the network layers. The network is composed by a first layer which performs convolutions of binary weights with analog inputs and a set of fully binarized hidden layers. This structure allows to remove the analog to digital converters in the image sensor since the first layer is able to process analog values. Hidden layers are arranged following an in-memory computing SRAM architecture: In this work, this architecture employs 8T bit cells to perform convolutions, although it can be accommodated to use other in-memory computing topologies from the literature. The proposed architecture has been synthesized at device level using a CMOS 180 nm technology to process 28x28 grayscale images. For this technology, the requirements of silicon area are reduced by a factor equal to the image height.

关键词： CMOS in memory computing computer vision deep neural network binary neural network

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Interconnects for DNA, Quantum, In-memory, and Optical computing: Insights From a Panel Discussion

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IEEE MICRO 2022年第3期42卷 40-49页

作者： Ganguly, Amlan Abadal, Sergi Thakkar, Ishan Jerger, Natalie Enright Riedel, Marc Babaie, Masoud Balasubramonian, Rajeev Sebastian, Abu Pasricha, Sudeep Taskin, Baris Rochester Inst Technol Comp Engn Rochester NY 14623 USA Univ Politecn Cataluna Barcelona 08034 Spain Univ Kentucky Elect & Comp Engn Lexington KY USA Univ Toronto Comp Architecture Toronto ON M5S 3G4 Canada Univ Minnesota Elect & Comp Engn Minneapolis MN 55455 USA Delft Univ Technol NL-2628 CD Delft Netherlands Univ Utah Sch Comp Salt Lake City UT 84112 USA IBM Res CH-8803 Zurich Switzerland Colorado State Univ Elect & Comp Engn Dept Ft Collins CO 80523 USA Drexel Univ Dept Elect & Comp Engn Philadelphia PA 19104 USA

The computing world is witnessing a proverbial Cambrian explosion of emerging paradigms propelled by applications, such as artificial intelligence, big data, and cybersecurity. The recent advances in technology to store digital data inside a deoxyribonucleic acid (DNA) strand, manipulate quantum bits (qubits), perform logical operations with photons, and perform computations inside memory systems are ushering in the era of emerging paradigms of DNA computing, quantum computing, optical computing, and in-memory computing. In an orthogonal direction, research on interconnect design using advanced electro-optic, wireless, and microfluidic technologies has shown promising solutions to the architectural limitations of traditional von-Neumann computers. In this article, experts present their comments on the role of interconnects in the emerging computing paradigms, and discuss the potential use of chiplet-based architectures for the heterogeneous integration of such technologies.

关键词： DNA Qubit Optical computing Wireless Communication Integrated Circuit Interconnections Deep Learning DNA computing Optical computing Quantum computing in memory computing Photonic Interconnects Wireless Interconnects

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Design and implementation of a charge-sharing in-memory-computing macro with sparse feature for quantized neural network

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MICROELECTRONICS JOURNAL 2024年 154卷

作者： Liu, Yihe Wang, Junjie Liu, Shuang Sun, Mingyuan Zhang, Xiaoyang Zhou, Jingtao Yan, Shiqin Pan, Ruicheng Hu, Hao Liu, Yang Univ Elect Sci & Technol China State Key Lab Thin Solid Films & Integrated Device 2006 Xiyuan Ave Chengdu 610054 Sichuan Peoples R China Chang Feng Mech & Elect Technol Acad Beijing 100089 Peoples R China Beijing Inst Remote Sensing Equipment Sci & Technol Millimeter Wave Lab Beijing 100854 Peoples R China

With the rapid development of artificial intelligence technology, in-memory computing has become a research hotspot. In this article, we propose an in-memory computing (IMC) architecture that achieves high energy efficiency and performance. Our work is based on the working mechanism of charge sharing, enabling configurable multi-bit Multiply-Accumulate operations. This work employs a unique bit-cell structure to implement sparse strategies at the bit-level in IMC arrays and compensates for errors caused by non-ideal effects, thus achieving better energy efficiency and performance. A hardware-aware quantification method and a hardware simulation model based on Pytorch have been proposed to evaluate the hardware mapping and compare with other charge domain IMC works. The MNIST and CIFAR-10 datasets have been used to validate algorithm models and chip performance, achieving accuracy rates of 97.6% and 90.5% respectively. The IMC chip was fabricated with a 180 nm CMOS process. The measurement shows that the chip achieves an energy efficiency of 41.8 TOPS/W.

关键词： in memory computing Artificial intelligence High energy efficiency

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Generation of Verified Programs for In-memory computing 25

Generation of Verified Programs for In-Memory Computing

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25th Euromicro Conference on Digital System Design (DSD)

作者： Froehlich, Saman Drechsler, Rolf Univ Bremen Grp Comp Architecture Bremen Germany DFKI GmbH Cyber Phys Syst Bremen Germany

ISBN: (纸本)9781665474047

In order to overcome the von Neumann bottleneck, recently the paradigm of in-memory computing has emerged. Here, instead of transferring data from the memory to the CPU for computation, the computation is directly performed within the memory. ReRAM, a resistance-based storage device, is a promising technology for this paradigm. Based on ReRAM, the PLiM computer architecture and LiM-HDL, an HDL for specifying PLiM programs have emerged. In this paper, we first present a novel levelization algorithm for LiM-HDL. Based on this novel algorithm, large circuits can be compiled to PLiM programs. Then, we present a verification scheme for these programs. This scheme is separated into two steps: (1) A proof of purity and (2) a proof of equivalence. Finally, in the experiments, we first apply our levelization algorithms to a well-known benchmark set, where we show that we can generate PLiM programs for large benchmarks, for which existing levelization algorithms fails. Then, we apply our proposed verification scheme to these PLiM programs.

关键词： in memory computing LiM HDL PLiM ReRAM RRAM

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Energy efficient in-memory computing to enable decentralised service workflow composition in support of multi-domain operations

Energy efficient in-memory computing to enable decentralised...

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Conference on Artificial Intelligence and Machine Learning for Multi-Domain Operations Applications III

作者： Bent, Graham Simpkin, Christopher Taylor, Ian Rahimi, Abbas Karunaratne, Geethan Abu Sebastian Millar, Declan Martens, Andreas Roy, Kaushik Cardiff Univ Crime & Secur Res Inst Cardiff Wales IBM Res Europe Zurich Switzerland IBM Res Europe Hursley England Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (数字)9781510643307

ISBN: (纸本)9781510643307

Future Multi-Domain Operations (MDO) will require the coordination of hundreds-even thousands-of devices and component services. This will demand the capability to rapidly discover the distributed devices/services and combine them into different workflow configurations, thereby creating the applications necessary to support changing mission needs. To meet these objectives, we envision a distributed Cognitive computing System (CCS) that consists of humans and software that work together as a 'Distributed Federated Brain'. Motivated by neuromorphic processing models, we present an approach that uses hyperdimensional symbolic semantic vector representations of the services/devices and workflows. We show how these can be used to perform decentralized service/device discovery and workflow composition in the context of a dynamic communications re-planning scenario. In this paper, we describe how emerging analogue AI 'In memory' and 'Near memory' computing devices can be used to efficiently perform some of the required hyperdimensional vector computation (HDC). We present an evaluation of the performance of an energy-efficient phase change memory device (PCM) that can perform the required vector operations and discuss how such devices could be used in energy-critical 'edge of network' tactical MDO operations.

关键词： Analogue AI in memory computing services workflow Hyperdimensional computing Semantic Vectors

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ReARTSim: an ReRAM ARray Transient Simulator with GPU optimized runtime acceleration

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NEUROMORPHIC computing AND ENGINEERING 2024年第1期4卷 014006-014006页

作者： Sui, Yu Yu, Tianhe Song, Shiming USA 1127 Munich Terrac Sunnyval NJ 94089 USA

The demand for computation driven by machine learning and deep learning applications has experienced exponential growth over the past five years (Sevilla et al 2022 2022 International Joint Conference on Neural Networks (IJCNN) (IEEE) pp 1-8), leading to a significant surge in computing hardware products. Meanwhile, this rapid increase has exacerbated the memory wall bottleneck within mainstream Von Neumann architectures (Hennessy and Patterson et al 2011 Computer architecture: a quantitative approach (Elsevier)). For instance, NVIDIA graphical processing units (GPUs) have gained nearly a 200x increase in fp32 computing power, transitioning from P100 to H100 in the last five years (NVIDIA Tesla P100 2023 (***/en-us/data-center/tesla-p100/);NVIDIA H100 Tensor Core GPU 2023 (***/en-us/data-center/h100/)), accompanied by a mere 8x scaling in memory bandwidth. Addressing the need to mitigate data movement challenges, process-in-memory designs, especially resistive random-access memory (ReRAM)-based solutions, have emerged as compelling candidates (Verma et al 2019 IEEE Solid-State Circuits Mag. 11 43-55;Sze et al 2017 Proc. IEEE 105 2295-329). However, this shift in hardware design poses distinct challenges at the design phase, given the limitations of existing hardware design tools. Popular design tools today can be used to characterize analog behavior via SPICE tools (PrimeSim HSPICE 2023 (***/implementation-and-signoff/ams-simulation/***)), system and logical behavior using Verilog tools (VCS 2023 (***/verification/simulation/***)), and mixed signal behavior through toolbox like CPPSIM (Meninger 2023 (***/Tutorials/wideband_fracn_***)). Nonetheless, the design of in-memory computing systems, especially those involving non-CMOS devices, presents a unique need for characterizing mixed-signal computing behavior across a large number of cells within a memory bank. This requirement f

关键词： ReRAM in memory computing transient simulation GPU acceleration AI simulation

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BitS-Net: Bit-Sparse Deep Neural Network for Energy-Efficient RRAM-Based Compute-In-memory

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第5期69卷 1952-1961页

作者： Karimzadeh, Foroozan Yoon, Jong-Hyeok Raychowdhury, Arijit Georgia Inst Technol Dept Elect & Comp Engn Atlanta GA 30332 USA Daegu Gyeongbuk Inst Sci & Technol DGIST Dept Informat & Commun Engn Daegu 42988 South Korea

The rising popularity of intelligent mobile devices and the computational cost of deep learning-based models call for efficient and accurate on-device inference schemes. We propose a novel model compression scheme that allows inference to be carried out using bit-level sparsity, which can be efficiently implemented using in-memory computing macros. In this paper, we introduce a method called BitS-Net to leverage the benefits of bit-sparsity (where the number of zeros are more than number of ones in binary representation of weight/activation values) when applied to compute-in-memory (CIM) with resistive RAM (RRAM) to develop energy efficient DNN accelerators operating in the inference mode. We demonstrate that BitS-Net improves the energy efficiency by up to 5x for ResNet models on the ImageNet dataset.

关键词： Computer architecture Quantization (signal) Microprocessors Computational modeling Training Resistance Neural networks Deep neural network quantization in memory computing DNN accelerator

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Realization of Reading-based Ternary Lukasiewicz Logic using Memristive Devices

Realization of Reading-based Ternary Lukasiewicz Logic using...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Liu, Feng Zhao, Xianyue Chen, Ziang Bengel, Christopher Du, Nan Menzel, Stephan Forschungszentrum Julich Peter Grunberg Inst PGI 7 Julich Germany Friedrich Schiller Univ Jena Inst Solid State Phys Jena Germany Rhein Westfal TH Aachen Inst Elect Mat 2 Aachen Germany Leibniz Inst Photon Technol Dept Quantum Detect Jena Germany

ISBN: (纸本)9798350330991;9798350331004

Memristive devices can not only be used as nonvolatile memories but also enable computation-in-memory (CIM) computing paradigms. CIM architectures show prospects in significantly reducing the data interaction time and energy consumption between processors and storage, thus addressing the bottleneck problem of the von Neumann architecture. Additionally, the capability of memristive devices to store multiple (resistance) states in one cell offer vast potential for CIM's multi-valued logic, as they greatly enhance data storage density and computational efficiency. In this study, a novel concept for ternary Lukasiewicz logic utilizing the voltage divider of two (anti-)serially connected memristive devices is proposed. As this approach does not require any switching in the computation process and features a straightforward circuit architecture, a low energy consumption per operation is achieved. In addition, the concept is crossbar-array compatible. The concept is validated by circuit simulations using the JART VCM v1b model that has been calibrated to experimental data of a Pt/Ta2O5/W memristive device.

关键词： ternary Lukasiewicz logic in memory computing memristance-input-voltage-output (MIVO) crossbar-array compatible

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