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19th IEEE-India-Council International Conference (INDICON)

作者： Appukuttan, Allen Thomas, Emmanuel Nair, Harinandan R. Hemanth, S. Dhanaraj, K. J. Azeez, Maleeha Abdul Natl Inst Technol Calicut Dept Elect & Commun Engn Calicut Kerala India

ISBN: (纸本)9781665473507

In recent years, AI/ML has been increasingly becoming a part of our daily lives and in the technology around us. With this increasing prevalence, they currently provide the most effective solutions to a wide range of image recognition, speech recognition, and natural language processing challenges. The demand for fast and efficient calculations of increasingly complex models has gained immense importance. One of the biggest technical limitations faced today is the Von Neumann bottleneck. However, the data movement between memory tiers can be reduced by incorporating in-memory computing modules into the architecture. The possibility of using specialized circuits to improve the efficiency of matrix multiplication was attempted on a small test neural network. We focus on using SRAM-based in-memory computing modules, that use binary weights and inputs which can offer a significant improvement to performance and efficiency without a heavy impact on the accuracy of the models.

关键词： in-memory computing Matrix multiplication Neural networks Static Random Access memory Von Neumann bottleneck

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in-memory computing based Accelerator for Transformer Networks for Long Sequences

In-Memory Computing based Accelerator for Transformer Networ...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Laguna, Ann Franchesca Kazemi, Arman Niemier, Michael Hu, X. Sharon Univ Notre Dame Dept Comp Sci & Engn Notre Dame IN 46556 USA

ISBN: (纸本)9783981926354

Transformer networks have outperformed recurrent neural networks and convolutional neural networks in various sequential tasks. However, scaling transformer networks for long sequences has been challenging because of memory and compute bottlenecks. Transformer networks are impeded by memory bandwidth limitations because of their low operation per byte ratio resulting in low utilization of GPU's computing resources. In-memory processing can mitigate memory bottlenecks by eliminating the transfer time between memory and compute units. Furthermore, transformer networks use neural attention mechanisms to characterize the relationships between sequence elements. Efficient hardware solutions have been proposed to implement efficient attention mechanisms, which include ternary content addressable memories (TCAM), crossbar arrays (XBars), and processing in-memory (PIM). However, these solutions do not implement a multi-head self-attention mechanism. We propose using a combination of XBars and CAMs to accelerate transformer networks. We improve the speed of transformer networks by (1) computing in-memory, thus minimizing the memory transfer overhead, (2) caching reusable parameters to reduce the number of operations, (3) exploiting the available parallelism in the attention mechanism, and (4) using locality sensitive hashing to filter the number of sequence elements by their importance. Our approach achieves a 200x speedup and 41x energy improvement for a sequence length of 4098.

关键词： Transformers crossbars TCAM LSH parallelization in-memory computing

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in-memory computing Architecture for Efficient Hardware Security 7

In-Memory Computing Architecture for Efficient Hardware Secu...

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IEEE 7th International Conference on Advanced Technologies, Signal and Image Processing (ATSIP)

作者： Ajmi, Hala Zayer, Fakhreddine Belgacem, Hamdi Univ Monastir Fac Sci Monastir Elect & Microelect Lab Monastir Tunisia Khalifa Univ Sci & Technol Khalifa Univ Abu Dhabi U Arab Emirates

ISBN: (纸本)9798350351491;9798350351484

This paper presents an innovative approach utilizing in-memory computing (IMC) for the development and integration of AES (Advanced Encryption Standard) cipher technique. Our research aims to enhance cybersecurity measures for a wide range of applications for IoT, such as robotic self-driving and several uses contexts. Memristor (MR) design optimized for in-memory processing is introduced. Our work highlights the development of a 4-bit state memristor device tailored for various range of arithmetic functions in a hardware prototype of AES system. Additionally, we propose a pipeline AES design aimed at harnessing extensive parallelism and ensuring compatibility with MR devices. This approach enhances hardware performance by by managing larger data amounts, accelerating computational, and achieving greater precision demands. Compared to traditional AES hardware, AES-IMC demonstrates an approximate 30 % improvement in power with a comparable throughput rate. Compared with the latest AES-based NVM engines, AES-IMC achieves an impressive 62 % improvement in throughput at similar power dissipation levels. The IMC-developed design will protect against unintentional incidents involving unmanned devices, reducing the risks associated with hostile assaults such as hijacking and illegal control of robots. This helps to reduce the possible economic and financial losses caused by incidents.

关键词： AES cipher memristive architecture Hardware security in-memory computing FPGA implementation

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in-memory computing Architectures for Big Data and Machine Learning Applications 9th

In-Memory Computing Architectures for Big Data and Machine L...

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9th International Conference, FDSE

作者： Snasel, Vaclav Tran Khanh Dang Pham, Phuong N. H. Kueng, Josef Kong, Lingping VSB Tech Univ Ostrava Fac Elect Engn & Comp Sci Ostrava Czech Republic Ho Chi Minh City Univ Food Ind HUFI Fac Informat Technol Ho Chi Minh City Vietnam Johannes Kepler Univ Linz Linz Austria

ISBN: (纸本)9789811980688;9789811980695

Traditional computing hardware is working to meet the extensive computational load presented by the rapidly growing Machine Learning (ML) and Artificial Intelligence algorithms such as Deep Neural Networks and Big Data. In order to get hardware solutions to meet the low-latency and high-throughput computational needs of these algorithms, Non-Von Neumann computing architectures such as in-memory computing (IMC) have been extensively researched and experimented with over the last five years. This study analyses and reviews works designed to accelerate Machine Learning task. We investigate different architectural aspects and directions and provide our comparative evaluations. We further discuss IMC research's challenges and limitations and present possible directions.

关键词： in-memory computing Machining learning Deep neural network In-memory accelerator

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A Universal, Analog, in-memory computing Primitive for Linear Algebra Using Memristors

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2021年第12期68卷 4889-4899页

作者： Mannocci, Piergiulio Pedretti, Giacomo Giannone, Elisabetta Melacarne, Enrico Sun, Zhong Ielmini, Daniele Politecn Milan Dipartimento Elettron Informaz & Bioingn I-20133 Milan Italy Hewlett Packard Labs Milpitas CA 95035 USA Peking Univ PKU Sch Integrated Circuits Inst Artificial Intelligence Beijing 100871 Peoples R China

The increasing demand for data-intensive computing applications, such as artificial intelligence (AI) and more specifically machine learning (ML), raises the need for novel computing hardware architectures capable of massive parallelism in performing core algebraic operations. Among the new paradigms, in-memory computing (IMC) with analogue devices is attracting significant interest for its large-scale integration potential, together with unrivaled speed and energy performance. Here, we present a fully-analogue, universal primitive capable of executing linear algebra operations such as regression, generalized least-square minimization and linear system solution with and without preconditioning. We study the impact of the main circuit parameters on accuracy and bandwidth with analytical closed-form expressions and SPICE simulations. Scaling challenges due to parasitic resistance/capacitance and their impact on key parameters such as bandwidth and accuracy are discussed. Finally, a comparison with existing solvers belonging to the same IMC framework is made to assess advantages and disadvantages of the proposed circuit.

关键词： Linear systems Integrated circuit modeling Linear regression Mathematical models Covariance matrices Bandwidth SPICE in-memory computing resistive memory hardware accelerator linear regression linear systems

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in-memory computing with Memristor Arrays 10

In-Memory Computing with Memristor Arrays

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10th IEEE International memory Workshop (IMW)

作者： Li, Can Belkin, Daniel Li, Yunning Yan, Peng Hu, Miao Ge, Ning Jiang, Hao Montgomery, Eric Lin, Peng Wang, Zhongrui Strachan, John Paul Barnell, Mark Wu, Qing Williams, R. Stanley Yang, J. Joshua Xia, Qiangfei Univ Massachusetts Amherst MA 01003 USA Hewlett Packard Enterprise Hewlett Packard Labs Palo Alto CA 94304 USA HP Inc HP Labs Palo Alto CA 94304 USA Swarthmore Coll Swarthmore PA 19081 USA Huazhong Univ Sci & Technol Wuhan Natl Lab Optoelect Wuhan 430074 Hubei Peoples R China US Air Force Res Lab Informat Directorate Rome NY 13441 USA

ISBN: (纸本)9781538652473

Memristors with tunable non-volatile resistance states offer the potential for in-memory computing that mitigates the von-Neumann bottleneck. We build a large scale memristor array by integrating a transistor array with Ta/HfO2 memristors that have stable multilevel resistance states and linear IV characteristic. With off-chip peripheral driving circuits, the memristor chip is capable of high-precision analog computing and online learning. We demonstrate a weight-update scheme that provides linear and symmetric potentiation and depression with no more than two pulses for each cell. We train the array as a single-layer fully-connected feedforward neural network for the WDBC data base and achieve 98% classification accuracy. We further partition the array into a two-layer network, which achieves 91.71% classification accuracy for MNIST database experimentally. The system demonstrates high defect tolerance and excellent speed-energy efficiency.

关键词： in-memory computing memristor RRAM online learning neural network

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Recent Advances in in-memory computing:Exploring Memristor and Memtransistor Arrays with 2D Materials

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Nano-Micro Letters 2024年第7期16卷 1-30页

作者： Hangbo Zhou Sifan Li Kah-Wee Ang Yong-Wei Zhang Institute of High Performance Computing(IHPC) Agency for ScienceTechnology and Research(A*STAR)1 Fusionopolis Way#16-16 ConnexisSingapore 138632Republic of Singapore Department of Electrical and Computer Engineering National University of Singapore4 Engineering Drive 3Singapore 117583Republic of Singapore Institute of Materials Research and Engineering Agency for ScienceTechnology and Research(A*STAR)2 Fusionopolis WaySingapore 138634Republic of Singapore

The conventional computing architecture faces substantial chal-lenges,including high latency and energy consumption between memory and processing *** response,in-memory computing has emerged as a promising alternative architecture,enabling computing operations within memory arrays to overcome these *** devices have gained significant attention as key components for in-memory computing due to their high-density arrays,rapid response times,and ability to emulate biological *** these devices,two-dimensional(2D)material-based memristor and memtransistor arrays have emerged as particularly promising candidates for next-generation in-memory computing,thanks to their exceptional performance driven by the unique properties of 2D materials,such as layered structures,mechanical flexibility,and the capability to form *** review delves into the state-of-the-art research on 2D material-based memristive arrays,encompassing critical aspects such as material selection,device perfor-mance metrics,array structures,and potential ***,it provides a comprehensive overview of the current challenges and limitations associated with these arrays,along with potential *** primary objective of this review is to serve as a significant milestone in realizing next-generation in-memory computing utilizing 2D materials and bridge the gap from single-device characterization to array-level and system-level implementations of neuromorphic computing,leveraging the potential of 2D material-based memristive devices.

关键词： 2D materials Memristors Memtransistors Crossbar array in-memory computing

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in-memory computing: Global Energy Consumption, Carbon Footprint, Technology, and Products Status Quo 24

In-Memory Computing: Global Energy Consumption, Carbon Footp...

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IEEE 24th International Conference on Nanotechnology (NANO)

作者： TaheriNejad, Nima TU Wien EclectX Team Vienna Austria Heidelberg Univ Heidelberg Germany

ISBN: (纸本)9798350386257;9798350386240

In this paper, we highlight and quantify the importance and potential role of In-memory Computation (IMC) and memory technologies in the future of humans' global footprint. To this end, we calculate the estimated energy consumption and carbon emission associated with the data movement inside computing systems and put them in perspective using tangible examples. Next, we review various memory technologies as well as their advantages and disadvantages (especially regarding their energy consumption), for usage in computing systems as memory and computing elements. We calculate what their impact is and what would be the potential savings of migrating towards emerging memory technologies. We discuss some of the challenges these emerging memory technologies face, before presenting the highlights of the IMC products on or near the market. This paper aims at providing an insight on the impact of IMC and memory technology on the society at large and clarify the importance of working on IMC and emerging memory technologies to lower the power consumption and overall footprint of computing systems. The status of IMC products show that while moving in the right direction, there is a substantial body of work to be done. We hope this will help engineers to better grasp the extent of the impact they can produce and motivate them further in the pursuit of better computing systems.

关键词： in-memory computing memory Technology Global Impact Energy Consumption Carbon Emission Industrial Products

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Room-Temperature Fabricated Multilevel Nonvolatile Lead-Free Cesium Halide Memristors for Reconfigurable in-memory computing

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ACS NANO 2022年第8期16卷 12979-12990页

作者： Su, Tsung-Kai Cheng, Wei-Kai Chen, Cheng-Yueh Wang, Wei-Chun Chuang, Yung-Tang Tan, Guang-Hsun Lin, Hao-Cheng Hou, Cheng-Hung Liu, Ching-Min Chang, Ya-Chu Shyue, Jing-Jong Wu, Kai-Chiang Lin, Hao-Wu Natl Tsing Hua Univ Dept Mat Sci & Engn Hsinchu 30013 Taiwan Acad Sinica Res Ctr Appl Sci Taipei 11529 Taiwan Natl Yang Ming Chiao Tung Univ Dept Comp Sci Hsinchu 30010 Taiwan Natl Tsing Hua Univ Frontier Res Ctr Fundamental & Appl Sci Matters Hsinchu 30013 Taiwan

Recently, conductive-bridging memristors based on metal halides, such as halide perovskites, have been demonstrated as promising components for brain-inspired hardware-based neuromorphic computing. However, realizing devices that simultaneously fulfill all of the key merits (low operating voltage, high dynamic range, multilevel non-volatile storage capability, and good endurance) remains a great challenge. Herein, we describe lead-free cesium halide memristors incorporating a MoOX interfacial layer as a type of conductive-bridging memristor. With this design, we obtained highly uniform and reproducible memristors that exhibited all-around resistive switching characteristics: ultralow operating voltages (< 0.18 V), low variations (< 30 mV), long retention times (> 106 s), high endurance (> 105, full on/off cycles), record-high on/off ratios (> 10(10), smaller devices having areas < 5 x 10(-4) mm2), fast switching (< 200 ns), and multilevel programming abilities (> 64 states). With these memristors, we successfully implemented stateful logic functions in a reconfigurable architecture and accomplished a high classification accuracy (ca. 90%) in the simulated hand-written-digits classification task, suggesting their versatility in future in-memory computing applications. In addition, we exploited the room-temperature fabrication of the devices to construct a fully functional three-dimensional stack of memristors, which demonstrates their potential of high-density integration desired for data-intensive neuromorphic computing. High-performance, environmentally friendly cesium halide memristors provide opportunities toward next-generation electronics beyond von Neumann architectures.

关键词： metal halide memristor perovskite multilevel nonvolatile in-memory computing

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A Flexible and Reliable RRAM-Based in-memory computing Architecture for Data-Intensive Applications

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IEEE TRANSACTIONS ON EMERGING TOPICS IN computing 2023年第3期11卷 736-748页

作者： Eslami, Nima Moaiyeri, Mohammad Hossein Shahid Beheshti Univ Fac Elect Engn Tehran *** Iran

This article proposes a practical, flexible, and reliable in-memory computing architecture for resistive-memory-based logic designs. Our design uses a new RRAM-based polymorphic in-memory logic gate implementing all 2-input Boolean logic functions to handle real-time applications like search engines. This design reduces the proposed architecture's power-delay product (PDP) compared to competing designs by utilizing the features of the RRAM device and the proposed reconfigurable sensing amplifier. Additionally, the simulation results on the ISCAS-89 and ITC-99 benchmarks at the 7nm technology node show that the suggested architecture's PDP is lower than the comparable state-of-the-art designs. A novel sense amplifier supporting all Boolean logic functions is also proposed to handle the applications with resistive-resistive-based inputs, such as search applications. After retrieving data from the main memory, the suggested sense amplifier computes the desired output. To assess the functionality of the suggested design in the presence of process variations, Monte Carlo simulations are conducted to authenticate the robustness and high-performance operation of the proposed design in different classes of resistive-memory-based logic in the presence of process variations. Our results further demonstrate that, compared to its counterpart, the suggested strategy dramatically reduces the energy consumption of the median, Max, and Min filters in real-world applications.

关键词： in-memory computing polymorphic gate process variations RRAM (resistive RAM)

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