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Low-Power Memristive Logic Device Enabled by Controllable Oxidation of 2D HfSe2 for in-memory computing

ADVANCED SCIENCE 2021年第15期8卷 e2005038页

作者： Liu, Long Li, Yi Huang, Xiaodi Chen, Jia Yang, Zhe Xue, Kan-Hao Xu, Ming Chen, Huawei Zhou, Peng Miao, Xiangshui Huazhong Univ Sci & Technol Sch Opt & Elect Informat Wuhan Natl Lab Optoelect Wuhan 430074 Peoples R China Fudan Univ Sch Microelect State Key Lab ASIC & Syst Shanghai 200433 Peoples R China

Memristive logic device is a promising unit for beyond von Neumann computing systems and 2D materials are widely used because of their controllable interfacial properties. Most of these 2D memristive devices, however, are made from semiconducting chalcogenides which fail to gate the off-state current. To this end, a crossbar device using 2D HfSe2 is fabricated, and then the top layers are oxidized into "high-k" dielectric HfSexOy via oxygen plasma treatment, so that the cell resistance can be remarkably increased. This two-terminal Ti/HfSexOy/HfSe2/Au device exhibits excellent forming-free resistive switching performance with high switching speed (<50 ns), low operation voltage (<3 V), large switching window (10(3)), and good data retention. Most importantly, the operation current and the power consumption reach 100 pA and 0.1 fJ to 0.1 pJ, much lower than other Hf-O based memristors. A functionally complete low-power Boolean logic is experimentally demonstrated using the memristive device, allowing it in the application of energy-efficient in-memory computing.

关键词： 2D HfSe2 in-memory computing low-power consumption memristors oxidation resistive switching

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Custom RISC-V architecture incorporating memristive in-memory computing

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AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2024年 187卷

作者： Mallios, Konstantinos Alexandros Tompris, Ioannis Passias, Athanasios Ntinas, Vasileios Fyrigos, Iosif-Angelos Sirakoulis, Georgios Ch. Democritus Univ Thrace Dept Elect & Comp Engn Kimeria 67100 Xanthi Greece Tech Univ Dresden Inst Circuits & Syst Fac Elect & Comp Engn D-01069 Dresden Germany

Due to the rise in data-intensive applications, the von Neumann bottleneck is increasingly restricting modern computer architectures, resulting to latency and energy consumption. Addressing this challenge necessitates a CMOS-compatible solution with high energy efficiency and significant parallelism. Utilizing resistive switching components within a 1T1R crossbar array and the application of Stanford RRAM model, this paper suggests an original method for in-memory computing. Moreover, this work shows a new way to advance the popular RISC-V architecture by including memristive crossbar array. It does this by adding a custom instruction set, special hardware blocks, and the Scouting Logic Scheme. These modifications serve both as a comprehensive testbed for the memory system and a proof of concept for the future integration of memristors in computing architectures. The proposed design undergoes extensive testing and power analysis to validate its functionality and performance under various conditions. The results demonstrate significant improvements in computational efficiency and energy savings, highlighting the potential of memristor-based in-memory computing systems to overcome current architectural limitations.

关键词： in-memory computing RRAM crossbar RISC-V

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ADC-Less Reprogrammable RRAM Array Architecture for in-memory computing

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2023年第12期31卷 2053-2060页

作者： Dongre, Ashvinikumar Boro, Bipul Trivedi, Gaurav Indian Inst Technol Elect & Elect Engn Dept Gauhati 781039 India

Nonvolatile memories, such as resistive random access memory (RRAM), for in-memory computing (IMC), have shown great potential in accelerating neural networks (NNs). However, existing IMC architectures rely on the area and power-hungry analog-to-digital converters (ADCs) for sensing the current, diminishing all the benefits of RRAM. Also, enhancing memory density is essential for implementing compact and efficient artificial intelligence (AI) systems. Implementing multiple states in a single memory cell decreases the resistance between states, making it difficult to sense the current. Thus, incorporating ADCs in multilevel cells (MLCs) further increases the design cost. This article proposes an ADC-less reprogrammable RRAM-based IMC architecture. The ADC-less sensing scheme converts the RRAM array current into its digital equivalent. The proposed scheme can distinguish RRAM resistive states equivalent to 4-bit/cell with a minimal resistance margin of 0.3 KS2 between two consecutive states. It is realized with only 12 transistors, the least among the state-of-the-art designs used in IMC architectures. This article also presents an MLC programming method, resulting in a 22% cycle-to-cycle and device-to-device variation-tolerant design with an average power consumption of 21.5 mu W, which is 60.18% less than the contemporary IMC architectures. Furthermore, the proposed current sensor (CS) requires only 12 transistors which is the least among the state-of-the-art works.

关键词： Computer architecture Microprocessors Transistors in-memory computing Sensors Capacitors Resistance Analog-to-digital converter (ADC)-less in-memory computing (IMC) multilevel cell (MLC) resistive random access memory (RRAM) variation-tolerant

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Van der Waals Ferroelectric Semiconductor Field Effect Transistor for in-memory computing

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ACS NANO 2023年第6期17卷 6095-6102页

作者： Liao, Junyi Wen, Wen Wu, Juanxia Zhou, Yaming Hussain, Sabir Hu, Haowen Li, Jiawei Liaqat, Adeel Zhu, Hongwei Jiao, Liying Zheng, Qiang Xie, Liming Natl Ctr Nanosci & Technol CAS Key Lab Standardizat & Measurement Nanotechnol Beijing 100190 Peoples R China Tsinghua Univ Dept Chem Beijing 100084 Peoples R China Univ Chinese Acad Sci Beijing 100049 Peoples R China Tsinghua Univ Sch Mat Sci & Engn Beijing 100084 Peoples R China

in-memory computing is a highly efficient approach for breaking the bottleneck of von Neumann architectures, i.e., reducing redundant latency and energy consumption during the data transfer between the physically separated memory and processing units. Herein we have designed a in-memory computing device, a van der Waals ferroelectric semiconductor (InSe) based metal-oxide-ferroelectric semiconductor field-effect transistor (MOfeS-FET). This MOfeS-FET integrates memory and logic functions in the same material, in which the out-of-plane (OOP) ferroelectric polarization in InSe is used for data storage and the semiconducting property is used for the logic computation. The MOfeS-FET shows a long retention time with high on/off ratios (>106), high program/erase (P/E) ratios (103), and stable cyclic endurance. Moreover, inverter, programmable NAND, and NOR Boolean logic operations with nonvolatile storage of the results have all been demonstrated using our approach. These findings highlight the potential of van der Waals ferroelectric semiconductor-based MOfeS-FETs in the in-memory computing and their potential of achieving size scaling beyond Moore's law.

关键词： van der Waals ferroelectric semiconductor InSe metal-oxide-ferroelectric semiconductor field-effect transistor in-memory computing

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SRAM-Based in-memory computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第6期69卷 2412-2422页

作者： Mu, Junjie Kim, Hyunjoon Kim, Bongjin Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore Univ Calif Santa Barbara Dept Elect & Comp Engn Santa Barbara CA 93106 USA

This paper presents a mixed-signal SRAM-based in-memory computing (IMC) macro for processing binarized neural networks. The IMC macro consists of 128x 128 (16K) SRAM-based bitcells. Each bitcell consists of a standard 6T SRAM bitcell, an XNOR-based binary multiplier, and a pseudo-differential voltage-mode driver (i.e., an accumulator unit). Multiply-and-accumulate (MAC) operations between 64 pairs of inputs and weights (stored in the first 64 SRAM bitcells) are performed in 128 rows of the macro, all in parallel. A weight-stationary architecture, which minimizes off-chip memory accesses, effectively reduces energy-hungry data communications. A row-by-row analog-to-digital converter (ADC) based on 32 replica bitcells and a sense amplifier reduces the ADC area overhead and compensates for nonlinearity and variation. The ADC converts the MAC result from each row to an N-bit digital output taking 2 $<^>{N}$ -1 cycles per conversion by sweeping the reference level of 32 replica bitcells. The remaining 32 replica bitcells in the row are utilized for offset calibration. In addition, this paper presents a pseudo-differential voltage-mode accumulator to address issues in the current-mode or single-ended voltage-mode accumulator. A test chip including a 16Kbit SRAM IMC bitcell array is fabricated using a 65nm CMOS technology. The measured energy- and area-efficiency is 741-87TOPS/W with 1-5bit ADC at 0.5V supply and 3.97TOPS/mm(2), respectively.

关键词： Random access memory Voltage Inverters Neural networks memory management Transistors Voltage control Mixed-signal in-memory computing binarized neural network multiply-and-accumulate voltage-mode SRAM

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A Fully Digital SRAM-Based Four-Layer in-memory computing Unit Achieving Multiplication Operations and Results Store

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2023年第6期31卷 776-788页

作者： Lin, Zhiting Zhang, Shaoying Jin, Qian Xia, Jianping Liu, Yunwei Yu, Kefeng Zheng, Jian Xu, Xiaoming Fan, Xing Li, Ke Tong, Zhongzhen Wu, Xiulong Lu, Wenjuan Peng, Chunyu Zhao, Qiang Anhui Univ AHU Sch Integrated Circuits Hefei 230601 Peoples R China Anhui Prov High Performance Integrated Circuit Eng Hefei 230601 Peoples R China Anhui Univ AHU Sch Integrated Circuits Hefei 230601 Peoples R China Beihang Univ Sch Integrated Circuit Sci & Engn Beijing 100191 Peoples R China

The separation of memory and arithmetic logic unit (ALU) in the von Neumann computing architecture hinders the development of big data and high-performance computing. in-memory computing (IMC) as a new computation method significantly reduces the latency and power consumption of data processing. In this study, we propose a fully digital static random access memory (SRAM)-based IMC architecture, which has the following advantages: 1) it simplifies multiplication to multicycle addition operations, reuses logic cells, and reduces hardware overhead;2) by adding a pair of nMOS transistors to achieve internal write-back, the computational efficiency is improved, and at the same time, the final result of the multiplication can be stored locally, eliminating the need to read the computational result immediately;and 3) this scheme can be easily expanded to multiplication operations with different bit widths, which provides good scalability. A 4-kb SRAM-IMC macro chip is manufactured using the SMIC 55-nm technology to realize 4-bit multiplication, with an energy efficiency of 51.4 TOPS/W (0.9 V) and a throughput of 234.3 GOPS/mm(2) . The proposed multiplication-accumulation architecture is applied to a neural network, which achieves 98.7% accuracy with the Mixed National Institute of Standards and Technology database (MNIST) dataset.

关键词： Computer architecture Adders Discharges (electric) Threshold voltage SRAM cells in-memory computing Arithmetic in-memory computing (IMC) multiplication operation Index Terms static random access memory (SRAM) von Neumann bottleneck write-back operation

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Circuits and Architectures for in-memory computing-Based Machine Learning Accelerators

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IEEE MICRO 2020年第6期40卷 8-21页

作者： Ankit, Aayush Chakraborty, Indranil Agrawal, Amogh Ali, Mustafa Roy, Kaushik Purdue Univ Elect & Comp Engn W Lafayette IN 47907 USA Purdue Univ Nanoelect Res Lab W Lafayette IN 47907 USA Purdue Univ W Lafayette IN 47907 USA

Machine learning applications, especially deep neural networks (DNNs) have seen ubiquitous use in computer vision, speech recognition, and robotics. However, the growing complexity of DNN models have necessitated efficient hardware implementations. The key compute primitives of DNNs are matrix vector multiplications, which lead to significant data movement between memory and processing units in today's von Neumann systems. A promising alternative would be colocating memory and processing elements, which can be further extended to performing computations inside the memory itself. We believe in-memory computing is a propitious candidate for future DNN accelerators, since it mitigates the memory wall bottleneck. In this article, we discuss various in-memory computing primitives in both CMOS and emerging nonvolatile memory (NVM) technologies. Subsequently, we describe how such primitives can be incorporated in standalone machine learning accelerator architectures. Finally, we analyze the challenges associated with designing such in-memory computing accelerators and explore future opportunities.

关键词： Random access memory Nonvolatile memory CMOS technology memory management Feature extraction Acceleration Machine learning in-memory computing architectures circuits

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GFlink: An in-memory computing Architecture on Heterogeneous CPU-GPU Clusters for Big Data

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2018年第6期29卷 1275-1288页

作者： Chen, Cen Li, Kenli Ouyang, Aijia Zeng, Zeng Li, Keqin Hunan Univ Coll Informat Sci & Engn Changsha 410082 Hunan Peoples R China Natl Supercomp Ctr Changsha Changsha 410082 Hunan Peoples R China Zunyi Normal Coll Dept Informat Engn Zunyi 563006 Guizhou Peoples R China ASTAR Inst Infocomm Res Singapore 138632 Singapore SUNY Coll New Paltz Dept Comp Sci New Paltz NY 12561 USA

The increasing main memory capacity and the explosion of big data have fueled the development of in-memory big data management and processing. By offering an efficient in-memory parallel execution model which can eliminate disk I/O bottleneck, existing in-memory cluster computing platforms (e.g., Flink and Spark) have already been proven to be outstanding platforms for big data processing. However, these platforms are merely CPU-based systems. This paper proposes GFlink, an in-memory computing architecture on heterogeneous CPU-GPU clusters for big data. Our proposed architecture extends the original Flink from CPU clusters to heterogeneous CPU-GPU clusters, greatly improving the computational power of Flink. Furthermore, we have proposed a programming framework based on Flink's abstract model, i.e., DataSet (DST), hiding the programming complexity of GPUs behind the simple and familiar high-level interfaces. To achieve high performance and good load-balance, an efficient JVM-GPU communication strategy, a GPU cache scheme, and an adaptive locality-aware scheduling scheme for three-stage pipelining execution are proposed. Extensive experiment results indicate that the high computational power of GPUs can be efficiently utilized, and the implementation on GFlink outperforms that on the original CPU-based Flink.

关键词： Big data GPGPU heterogeneous cluster in-memory computing OpenCL

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Efficient Image Processing via Memristive-Based Approximate in-memory computing

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2024年第11期43卷 3312-3323页

作者： Seiler, Fabian TaheriNejad, Nima Tech Univ Wien TU Wien A-1040 Vienna Austria Heidelberg Univ D-69117 Heidelberg Germany

Image processing algorithms continue to demand higher performance from computers. However, computer performance is not improving at the same rate as before. In response to the current challenges in enhancing computing performance, a wave of new technologies and computing paradigms is surfacing. Among these, memristors stand out as one of the most promising components due to their technological prospects and low power consumption. With efficient data storage capabilities and their ability to directly perform logical operations within the memory, they are well-suited for in-memory computation (IMC). Approximate computing emerges as another promising paradigm, offering improved performance metrics, notably speed. The tradeoff for this gain is the reduction of accuracy. In this article, we are using the stateful logic material implication (IMPLY) in the semi-serial topology and combine both the paradigms to further enhance the computational performance. We present three novel approximated adders that drastically improve speed and energy consumption with an normalized mean error distance (NMED) lower than 0.02 for most scenarios. We evaluated partially approximated Ripple carry adder (RCA) at the circuit-level and compared them to the State-of-the-Art (SoA). The proposed adders are applied in different image processing applications and the quality metrics are calculated. While maintaining acceptable quality, our approach achieves significant energy savings of 6%-38% and reduces the delay (number of computation cycles) by 5%-35%, demonstrating notable efficiency compared to exact calculations.

关键词： Measurement Energy consumption Accuracy Power demand Image processing Approximation algorithms Topology Computational efficiency Logic Adders Approximate image processing IMPLY in-memory computing memristor

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Compressed Sensing With Approximate Message Passing Using in-memory computing

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2018年第10期65卷 4304-4312页

作者： Le Gallo, Manuel Sebastian, Abu Cherubini, Giovanni Giefers, Heiner Eleftheriou, Evangelos IBM Res Zurich Cloud & Comp Infrastruct CH-8803 Ruschlikon Switzerland

in-memory computing is a promising non-von Neumann approach where certain computational tasks are performed within resistive memory units by exploiting their physical attributes. In this paper, we propose a new method for fast and robust compressed sensing (CS) of sparse signals with approximate message passing recovery using in-memory computing. The measurement matrix for CS is encoded in the conductance states of resistive memory devices organized in a crossbar array. In this way, the matrix-vector multiplications associated with both the compression and recovery tasks can be performed by the same crossbar array without intermediate data movements at potential O(1) time complexity. For a signal of size N, the proposed method achieves a potential O(N)-fold recovery complexity reduction compared with a standard software approach. We show the array-level robustness of the scheme through large-scale experimental demonstrations using more than 256k phase-change memory devices.

关键词： Approximate message passing (AMP) compressed sensing (CS) in-memory computing phase-change memory (PCM)

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