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Mitigating RC-Delay Induced Accuracy Loss in Analog in-memory computing: A Non-Compromising Approach

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2024年第4期70卷 7544-7550页

作者： Zhu, Saike Lu, Cimang Qiu, Xiang Gao, Shifan Ding, Xiang Kim, Youngseo Zhao, Yi Zhejiang Univ Coll Elect Engn & Informat Sci Hangzhou 310027 Peoples R China Zhejiang Univ Int Joint Innovat Ctr Haining 314400 Peoples R China China Nanhu Acad Elect & Informat Technol Sensing Storage Comp Integrated Lab Jiaxing 314001 Peoples R China Flash Bill Semicond Co Ltd Algorithm & Compiler Design Dept Shanghai 201210 Peoples R China East China Normal Univ Sch Integrated Circuits Shanghai 200241 Peoples R China

The Internet of Things (IoT) has proliferated ubiquitous information exchange between the physical and cyber worlds through consumer electronics, with a focus on moving computing power to edge terminals. computing-in-memory (CIM) technology has emerged as a competitive candidate for edge computing because of its low power consumption and high performance. In order to achieve accurate inference for neural network models, it is crucial to comprehend the source of errors in the CIM-based analog computing paradigm. In this work, we analyzed the impact of random noises and output stabling times on the Programmable Linear Random Access memory (PLRAM)-based CIM chip. Experimental results show that the impact of random noise is negligible. The output stabling time can be treated as RC delay, which is related to the weight distribution. We proposed a weight reordering strategy to achieve better performance without sacrificing computation accuracy. Experiments with a commercial 11-keyword speech recognition model show a 74.4% runtime reduction while maintaining a 95.6% classification accuracy.

关键词： Accuracy Delays Noise Speech recognition in-memory computing Consumer electronics Computer architecture Compute-in-memory (CIM) memristor flash memory resistance-capacitance delay (RC delay)

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A Novel Oscillation-Based Reconfigurable in-memory computing Scheme With Error Correction

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IEEE TRANSACTIONS ON MAGNETICS 2021年第2期57卷 1-10页

作者： Muench, Christopher Sayed, Nour Bishnoi, Rajendra Tahoori, Mehdi Karlsruhe Inst Technol Dept Comp Sci Chair Dependable Nano Comp CDNC D-76131 Karlsruhe Germany Delft Univ Technol Comp Engn Lab NL-2628 CD Delft Netherlands

in-memory computing promises to overcome memory and power walls by allowing efficient computing of operations inside the memory without the need to explicitly transfer operands back and forth to the processor core. This paradigm is enabled by emerging resistive memory technology and the adjustment of the memory periphery to perform the computation. The existing methods to perform in-memory calculations are either hound to a specific technology or do not scale well for complex multi-input functions. In this article, we propose a new technique for in-memory computing using resistive devices to calculate the symmetric Boolean logic operations for any number of inputs. In our proposed method, we first convert the equivalent resistance state that is generated by storing devices to an electrical oscillation, and later, time-based sensing for these oscillations is employed to generate the required output. Since the computation using our proposed technique is based on the oscillations, it can be easily tuned for different computation tasks depending on applications. This is used to implement an efficient column-wise error-correction code (ECC) for in-memory computing. We have performed extensive Monte Carlo simulations to confirm the functionality of our proposed method in the presence of process variation. Compared with state-of-the-art comparative-based schemes, for a two-bit in-memory XOR computation, our proposed technique can improve dynamic energy by 41% and additionally scales well for more number of inputs. Results show a reduction of the parity overhead by 10% in our evaluated memory and an area reduction of 21% compared with conventional ECC circuits.

关键词： Error-correction code (ECC) in-memory computing reliability resistive random access memory (ReRAM) spin-transfer torque magnetic RAM (STT-MRAM)

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Accelerating Maximum-Likelihood Detection in Massive MIMO: A New Paradigm With Memristor Crossbar Based in-memory computing Circuit

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IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY 2024年第12期73卷 19745-19750页

作者： Ren, Yi-Hang Yang, Shaoshi Bi, Jia-Hui Zhang, Yu-Xin Beijing Univ Posts & Telecommun Sch Informat & Commun Engn Beijing 100876 Peoples R China Minist Educ Key Lab Universal Wireless Commun Beijing 100876 Peoples R China Minist Educ Key Lab Math & Informat Networks Beijing 100876 Peoples R China

Massive multi-input multi-output (MIMO) signal processing algorithms heavily rely on high-dimension matrix operations, which impose excessively high computational complexity. Moreover, in the post-Moore era, the performance of the classical von Neumann computing architecture is facing severe limitations. The memristor crossbar based in-memory computing holds the potential to break the memory wall and enhance the circuit's energy efficiency by orders-of-magnitude. In this paper we present a memristor crossbar based circuit design for performing the optimal maximum likelihood (ML) MIMO detection with high computation parallelism at the base station equipped with a large-scale antenna array. Simulation results show that, despite considering the circuit programming error and the memristor bit-precision, the bit error rate (BER) of the proposed circuit is almost the same as that achieved by the digital computer. Moreover, the proposed circuit achieves roughly the same level of computing performance as the NVIDIA QUADRO GV100, but with about 40 times higher energy efficiency.

关键词： Memristors Vectors Detectors Circuit synthesis Resistance Massive MIMO Integrated circuit modeling Laboratories maximum-likelihood detection memristor crossbar in-memory computing memristor crossbar in-memory computing

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Realization of flexible in-memory computing in a van der Waals ferroelectric heterostructure tri-gate transistor

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Nano Research 2024年第3期17卷 1886-1892页

作者： Xinzhu Gao Quan Chen Qinggang Qin Liang Li Meizhuang Liu Derek Hao Junjie Li Jingbo Li Zhongchang Wang Zuxin Chen School of Semiconductor Science and Technology South China Normal UniversityFoshan 528225China Guangdong Provincial Key Laboratory of Chip and Integration Technology Guangzhou 510631China Institute of Solid State Physics Hefei Institutes of Physical Science Chinese Academy of SciencesHefei 230601China School of Science STEM CollegeRMIT UniversityMelbourne 3000Australia CAS Key Laboratory of Functional Materials and Devices for Special Environments Xinjiang Technical Institute of Physics&ChemistryChinese Academy of SciencesUrumqi 830011China Center of Materials Science and Optoelectronics Engineering University of Chinese Academy of SciencesBeijing 100049China College of Optical Science and Engineering Zhejiang UniversityHangzhou 310027China International Iberian Nanotechnology Laboratory(INL) Av.Mestre Jose Veiga s/nBraga 4715-330Portugal

Combining logical function and memory characteristics of transistors is an ideal strategy for enhancing computational efficiency of transistor ***,we rationally design a tri-gate two-dimensional(2D)ferroelectric van der Waals heterostructures device based on copper indium thiophosphate(CuInP_(2)S_(6))and few layers tungsten disulfide(WS_(2)),and demonstrate its multi-functional applications in multi-valued state of data,non-volatile storage,and logic *** co-regulating the input signals across the tri-gate,we show that the device can switch functions flexibly at a low supply voltage of 6 V,giving rise to an ultra-high current switching ratio of 107 and a low subthreshold swing of 53.9 mV/*** findings offer perspectives in designing smart 2D devices with excellent functions based on ferroelectric van der Waals heterostructures.

关键词： two-dimensional(2D)ferroelectric heterostructure tri-gate polymorphic regulation in-memory computing

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MARADIV: Library of MAGIC-Based Approximate Restoring Array Divider Benchmark Circuits for in-memory computing Using Memristors

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2023年第7期70卷 2635-2639页

作者： Jha, Chandan Kumar Ahmadi-Pour, Sallar Drechsler, Rolf German Res Ctr Artificial Intelligence DFKI Dept Cyber Phys Syst D-28359 Bremen Germany Univ Bremen Inst Comp Sci D-28359 Bremen Germany German Res Ctr Artificial Intelligence DFKI D-28359 Bremen Germany

Among various arithmetic circuits, dividers are one of the costliest in terms of area, energy, and delay. Hence, approximate divider designs have been implemented to reduce their cost for error-resilient applications. However, approximate dividers based on memristors for in-memory computing (IMC) have not received any attention. In this brief, we propose a library of 16 by 8 approximate restoring array dividers suitable for memristor-based IMC that can be used as benchmark circuits. We developed these benchmark circuits by performing an exhaustive design space exploration based on functional approximation. We used the state-of-the-art mapping tool, SIMPLER, to perform the mapping of the divider design to the memristor crossbar. We identified the Pareto optimal approximate divider designs based on the MAGIC design style with varying output qualities. We compare our Pareto optimal designs with the existing state-of-the-art CMOS-based approximate divider designs when mapped to IMCs. We also performed a case study on two image processing applications. Overall we propose MARADIV, a library of MAGIC design style-based approximate restoring array divider benchmark circuits tailored for memristor-based IMC. We believe that MARADIV's benchmark designs can be used for future research in this direction. Hence, all Pareto optimal approximate restoring array divider designs will be made available at https://***/agra-uni-bremen/tcasii2022-maradiv-lib.

关键词： Approximate computing approximate restoring array divider in-memory computing memristors

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Programmable in-memory computing Circuit for Solving Combinatorial Matrix Operation in One Step

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第7期70卷 2916-2928页

作者： Hong, Qinghui Man, Shen Sun, Jingru Du, Sichun Zhang, Jiliang Hunan Univ Coll Comp Sci & Elect Engn Changsha 410082 Peoples R China Chinese Acad Sci Aerosp Informat Res Inst Beijing 100089 Peoples R China Hunan Univ Coll Semicond Coll Integrated Circuits Changsha 410082 Peoples R China

Matrix operations are widely used in practical engineering, but the traditional processing methods rely on the loop iterations and neural network algorithm on the software, requiring a long time to calculate. To address such problem, this paper proposes full hardware in-memory computing circuits based on programmable memristor unit array that can solve combinatorial matrix operations of any order in just one step. First, two basic circuit modules are introduced, which can respectively solve matrix multiplication and matrix equation. Further, the basic modules can be linked to solve combinatorial matrix operations with different forms. It's worth noting that every module can parallel program the value of each memristor in the memristor unit array and complete one-step computation by hardware. Then, some matrix operations are given in the paper as examples to prove the high accuracy of proposed method, where the average accuracy rate achieves 99%. The PSPICE simulation results demonstrate that the processing speed is improved enormously according to the comparison of hardware and software. Moreover, the proposed method has broad application prospect in practical engineering, such as using designed combinational circuit to solve domain shift problem in zero-shot learning, which greatly accelerates the training process of zero-shot learning.

关键词： Memristors Mathematical models Hardware Threshold voltage Computational modeling Integrated circuit modeling in-memory computing Memristor matrix operation circuit design Sylvester equation zero-shot learning

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A Monolithic 3-D Integration of RRAM Array and Oxide Semiconductor FET for in-memory computing in 3-D Neural Network

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2020年第12期67卷 5322-5328页

作者： Wu, Jixuan Mo, Fei Saraya, Takuya Hiramoto, Toshiro Kobayashi, Masaharu Univ Tokyo Inst Ind Sci Tokyo 1530041 Japan Univ Tokyo Dept Engn Syst Design Res Ctr D Lab Tokyo 1530041 Japan

We have monolithically integrated resistance random access memory (RRAM) array with oxide semiconductor channel access transistor in 3-D stack, achieved uniform memory characteristics of 1T1R cells at each layer, and demonstrated basic functionality of XNOR operation as in-memory computing for binary neural network (BNN) artificial intelligence (AI) applications. The integrated TiN/Ti/HfO2/Ti stack RRAM shows high on/off ratio with stable retention and endurance properties. The indium gallium zinc oxide (IGZO) channel field-effect transistor (FET) works as an access transistor, which realized the low-temperature process, high mobility, and high drive current for RRAM. With the peripheral circuit, we demonstrate the XNOR operation using a pair of 1T1R cells. The impact of RRAM bit error rate on neural network is also investigated, which indicates the property of error-resilience in BNN. The 3-D neural network built by this architecture has high potential to enable area-efficient, low-power, and low-latency computing.

关键词： Field effect transistors Resistance Neural networks Logic gates Hafnium oxide Voltage measurement Electrodes 3-D stack in-memory computing neural network oxide semiconductor resistance random access memory (RRAM) array

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Vesti: Energy-Efficient in-memory computing Accelerator for Deep Neural Networks

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2020年第1期28卷 48-61页

作者： Yin, Shihui Jiang, Zhewei Kim, Minkyu Gupta, Tushar Seok, Mingoo Seo, Jae-Sun Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA Columbia Univ Dept Elect Engn New York NY 10027 USA Synopsys Mountain View CA 94043 USA

To enable essential deep learning computation on energy-constrained hardware platforms, including mobile, wearable, and Internet of Things (IoT) devices, a number of digital ASIC designs have presented customized dataflow and enhanced parallelism. However, in conventional digital designs, the biggest bottleneck for energy-efficient deep neural networks (DNNs) has reportedly been the data access and movement. To eliminate the storage access bottleneck, new SRAM macros that support in-memory computing have been recently demonstrated. Several in-SRAM computing works have used the mix of analog and digital circuits to perform XNOR-and-ACcumulate (XAC) operation without row-by-row memory access and can map a subset of DNNs with binary weights and binary activations. In the single array level, large improvement in energy efficiency (e.g., two orders of magnitude improvement) has been reported in computing XAC over digital-only hardware performing the same operation. In this article, by integrating many instances of such in-memory computing SRAM macros with an ensemble of peripheral digital circuits, we architect a new DNN accelerator, titled Vesti. This new accelerator is designed to support configurable multibit activations and large-scale DNNs seamlessly while substantially improving the chip-level energy-efficiency with favorable accuracy tradeoff compared to conventional digital ASIC. Vesti also employs double-buffering with two groups of in-memory computing SRAMs, effectively hiding the row-by-row write latencies of in-memory computing SRAMs. The Vesti accelerator is fully designed and laid out in 65-nm CMOS, demonstrating ultralow energy consumption of < 20 nJ for MNIST classification and < 40 mu J for CIFAR-10 classification at 1.0-V supply.

关键词： Deep learning accelerator deep neural networks (DNNs) double-buffering in-memory computing SRAM

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Hafnium Oxide-Based Ferroelectric Devices for in-memory computing: Resistive and Capacitive Approaches

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ACS APPLIED ELECTRONIC MATERIALS 2024年第8期6卷 5391-5401页

作者： Lee, Minjong Narayan, Dushyant M. Kim, Jin-Hyun Le, Dan N. Shirodkar, Soham Park, Seongbin Kang, Jongmug Lee, Seungbin Ahn, Youngbae Ryu, Seung Wook Kim, Jiyoung Kim, Si Joon Univ Texas Dallas Dept Elect & Comp Engn Richardson TX 75080 USA Univ Colorado Dept Phys Boulder CO 80309 USA Univ Texas Dallas Dept Mat Sci & Engn Richardson TX 75080 USA Kangwon Natl Univ Dept Elect & Elect Engn Chunchon 24341 Gangwon Do South Korea Kangwon Natl Univ Dept BIT Med Convergence Chunchon 24341 Gangwon Do South Korea SK Hynix Inc R&D Div Icheon 17336 South Korea

The integration of ferroelectric hafnium oxide (HfO2) into semiconductor device structures has been a breakthrough in the development of state-of-the-art in-memory computing (IMC) technology. The high compatibility of ferroelectric HfO2 with backend-of-the-line (BEOL) as well as conventional complementary metal-oxide-semiconductor (CMOS) process technologies enables the development of highly efficient embedded IMC applications. In this work, we consider both resistive and capacitive approaches to the realization of IMC-compatible devices using ferroelectric HfO2. Process optimization and device integration concepts based on ferroelectric HfO2 are presented in this context. This Spotlight on Applications also reviews the reliability and reproducibility of HfO2-based ferroelectric devices. IMC architectures involving resistive systems are well established and mature. We discuss the capabilities and remarkable progress toward the integration of memristive ferroelectric HfO2 devices in these IMC architectures. Special attention is also given to the recently emerged ferroelectric capacitor (Fe-Cap)-based memcapacitive systems, which offer low-power consumption based on their open-circuit nature. Distinguished by their nondestructive readout capability, Fe-Caps stand out from other capacitive memories that require switching memory states and refresh cycles during access operations. Finally, we compare the electrical performance of Fe-Cap devices with other memristive technologies for IMC applications. This provides insights into the potential of ferroelectric HfO2-based devices for the development of highly efficient and advanced IMC systems.

关键词： ferroelectric hafnium oxide in-memory computing ferroelectric capacitor nondestructive readout memcapacitive system

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Enabling Energy-Efficient in-memory computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array

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IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 2023年第1期13卷 445-455页

作者： Soundrapandiyan, Kavitha Vishvakarma, Santosh Kumar Reniwal, Bhupendra Singh IIITDM Kancheepuram Dept Elect & Commun Chennai 600127 India Indian Inst Technol Indore Dept Elect Engn Indore 453552 Madhya Pradesh India Indian Inst Technol IIT Jodhpur Dept Elect Engn Jodhpur 342030 Rajasthan India

With the increasing gap between processing speed and memory bandwidth necessity for in/near-memory computing has emerged, to ensure high-performance, energy-efficient computing for data-intensive applications at the edge. This work proposes a feasible SRAM compute cache with a sense amplifier (SA) based approach to perform in-/near memory Boolean computations with a novel reconfigurable assist sense amplifier (RASA). The RASA exploits assist transistors to achieve NAND, NOR and XNOR operations without affecting the transparency of normal read leading to fast and reliable sensing with only one SA. This effectively eliminates the need for two SAs in comparison to state-of-the-art solutions. The proposed work improves memory density and reduces cost-per-bit by leveraging the SA-based approach because existing solutions lead to significant area overhead/cell which reflects overhead multiply by the number of cells/column. The RASA provides flexibility to accommodate more cells per column at the architecture level. Extensive Monte-Carlo analysis is performed to verify the feasibility of the proposed circuit in commercial 65nm UMC technology under iso-SA area and iso-yield conditions. Simulations indicate a 34.34%, 84.87%, 81.21%, 75.46% improvement in energy, and a 71.30%, 43.36%, 32.49%, 17.44% improvement in throughput leading to a reduction of 60.97%, 91.37%, 87.22%, 79.62% in energy-delay product with respect to CLSA (Dong et al., 2018), CSRAM (Chen et al., 2021), RRCSA (Rajput et al., 2022) and the ADSA (Agrawal et al., 2018) respectively. An improvement in the area of SA by 36.512% is achieved with respect to RRCSA.

关键词： Random access memory Computer architecture in-memory computing Decoding Bandwidth Arithmetic Transistors Assist device sense amplifier in memory computing digital Boolean logic

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