检索结果-内蒙古大学图书馆

Anonymizing Big Data Streams Using in-memory processing: A Novel Model Based on One-time Clustering

JOURNAL OF SIGNAL processing SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2024年第6-7期96卷 333-356页

作者： Shamsinejad, Elham Banirostam, Touraj Pedram, Mir Mohsen Rahmani, Amir Masoud Islamic Azad Univ Dept Comp Engn Cent Tehran Branch Tehran Iran Kharazmi Univ Fac Engn Dept Elect & Comp Engn Tehran Iran Islamic Azad Univ Dept Comp Engn Sci & Res Branch Tehran Iran

Big data privacy preservation is a critical challenge for data mining and data analysis. Existing methods for anonymizing big data streams using k-anonymity algorithms may cause high data loss, low data quality, and identity disclosure. In this paper, we propose a novel model for anonymizing big data streams using in-memory processing. The model uses a Spark framework to parallelize the anonymization process and a one-time clustering algorithm to avoid multiple iterations and allocate the data to optimal clusters. We evaluate the performance and effectiveness of the model using a real-world dataset and compare it with three popular k-anonymity algorithms: CRUE, Mean-Shift, and DBSCAN. The results show that the model has the lowest data loss and the highest data quality for different data sizes and k-values. The model is scalable, robust, adaptable, and flexible. The model can provide better data for data mining and data analysis while protecting data privacy and preventing data disclosure.

关键词： Big data Anonymity in-memory processing One-time clustering Data loss

来源：评论

学校读者我要写书评

暂无评论

CRIMP: Compact & Reliable DNN Inference on in-memory processing via Crossbar-Aligned Compression and Non-ideality Adaptation

引用

ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 2023年第5期22卷 1-25页

作者： Huai, Shuo Kong, Hao Luo, Xiangzhong Li, Shiqing Subramaniam, Ravi Makaya, Christian Lin, Qian Liu, Weichen Nanyang Technol Univ Sch Comp Sci & Engn Singapore Singapore HP Inc Palo Alto CA USA

Crossbar-based in-memory processing (IMP) accelerators have been widely adopted to achieve high-speed and low-power computing, especially for deep neural network (DNN) models with numerous weights and high computational complexity. However, the floating-point (FP) arithmetic is not compatible with crossbar architectures. Also, redundant weights of current DNN models occupy too many crossbars, limiting the efficiency of crossbar accelerators. Meanwhile, due to the inherent non-ideal behavior of crossbar devices, like write variations, pre-trained DNN models suffer from accuracy degradation when it is deployed on a crossbar-based IMP accelerator for inference. Although some approaches are proposed to address these issues, they often fail to consider the interaction among these issues, and introduce significant hardware overhead for solving each issue. To deploy complex models on IMP accelerators, we should compact the model and mitigate the influence of device non-ideal behaviors without introducing significant overhead from each *** this paper, we first propose to reuse bit-shift units in crossbars for approximately multiplying scaling factors in our quantization scheme to avoid using FP processors. Second, we propose to apply kernel-group pruning and crossbar pruning to eliminate the hardware units for data aligning. We also design a zerorize-recover training process for our pruning method to achieve higher accuracy. Third, we adopt the runtime-aware non-ideality adaptation with a self-compensation scheme to relieve the impact of non-ideality by exploiting the feature of crossbars. Finally, we integrate these three optimization procedures into one training process to form a comprehensive learning framework for co-optimization, which can achieve higher accuracy. The experimental results indicate that our comprehensive learning framework can obtain significant improvements over the original model when inferring on the crossbar-based IMP accelerator, with an a

关键词： in-memory processing pruning quantization ReRAM non-ideality

来源：评论

学校读者我要写书评

暂无评论

Reducing Smart Phone Environmental Footprints with in-memory processing

Reducing Smart Phone Environmental Footprints with In-Memory...

引用

2024 International Conference on Hardware/Software Codesign and System Synthesis

作者： Yang, Zhuoping Zhang, Wei Ji, Shixin Zhou, Peipei Jones, Alex K. Brown Univ Sch Engn Providence RI 02912 USA SUNY Syracuse Dept EECS Syracuse NY USA

ISBN: (纸本)9798350356403;9798350356397

Smart phones have revolutionized the availability of computing to the consumer. Recently, smart phones have been aggressively integrating artificial intelligence (AI) capabilities into their devices. The custom designed processors for the latest phones integrate incredibly capable and energy efficient graphics processors (GPUs) and tensor processors (TPUs) to accommodate this emerging AI workload and on-device inference. Unfortunately, smart phones are far from sustainable and have a substantial carbon footprint that continues to be dominated by environmental impacts from their manufacture and far less so by the energy required to power their operation. In this paper we explore the possibility of reversing the trend to increase the dedicated silicon dedicated to emerging application workloads in the phone. Instead we consider how in-memory processing using the DRAM already present in the phone could be used in place of dedicated GPU/TPU devices for AI inference. We explore the potential savings in embodied carbon that could be possible with this tradeoff and provide some analysis of the potential of inmemory computing to compete with these accelerators. While it may not be possible to achieve the same throughput, we suggest that the responsiveness to the user may be sufficient using inmemory computing, while both the embodied and operational carbon footprints could be improved. Our approach can save circa 10-15 kgCO(2)e.

关键词： sustainability embodied carbon in-memory processing AI inference

来源：评论

学校读者我要写书评

暂无评论

Selecting Efficient Cluster Resources for Data Analytics: When and How to Allocate for in-memory processing? 23

Selecting Efficient Cluster Resources for Data Analytics: Wh...

引用

35th International Conference on Scientific and Statistical Database Management, (SSDBM)

作者： Will, Jonathan Thamsen, Lauritz Scheinert, Dominik Kao, Odej Tech Univ Berlin Berlin Germany Univ Glasgow Glasgow Lanark Scotland

ISBN: (纸本)9798400707469

Distributed dataflow systems such as Apache Spark or Apache Flink enable parallel, in-memory data processing on large clusters of commodity hardware. Consequently, the appropriate amount of memory to allocate to the cluster is a crucial consideration. In this paper, we analyze the challenge of efficient resource allocation for distributed data processing, focusing on memory. We emphasize that in-memory processing with in-memory data processing frameworks can undermine resource efficiency. Based on the findings of our trace data analysis, we compile requirements towards an automated solution for efficient cluster resource allocation.

关键词： Distributed Dataflows Resource Allocation Resource Efficiency in-memory processing On-Disk processing

来源：评论

学校读者我要写书评

暂无评论

FeMAT: Exploring in-memory processing in Multifunctional FeFET-based memory Array 37

FeMAT: Exploring In-Memory Processing in Multifunctional FeF...

引用

37th IEEE International Conference on Computer Design (ICCD)

作者： Zhang, Xiaoyu Chen, Xiaoming Han, Yinhe Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing Peoples R China Univ Chinese Acad Sci Sch Comp Sci & Technol Beijing Peoples R China

ISBN: (纸本)9781538666487

The performance gap between the processors and the main memory is continuously widening, known as the memory wall bottleneck. Emerging nonvolatile devices have the ability of in-memory processing, and thus, have the potential to partially alleviate the memory wall bottleneck. People have adopted nonvolatile devices to build various accelerators that are targeted at different problems and applications. In this work, we adopt one of the emerging nonvolatile devices, the ferroelectric field-effect transistor (FeFET), to build a multi-functional in-memory processing unit, which is named FeMAT. From a structural point of view, FeMAT is an FeFET-based memory array composed of 3T-based cells. From a functional point of view, FeMAT not only is a nonvolatile memory, but also can perform some logic operations (i.e., the processing-in-memory (PIM) mode), binary convolutions (i.e., the binary convolutional neural network (BCNN) acceleration mode) and content searching (i.e., the ternary content-addressable memory (TCAM) mode) in the memory. These functions are seamlessly fused into the FeFET-based memory array and can be configured online without changing the circuit structure. Superior energy efficiency is demonstrated by our experiments and comparisons with a resistive random-access memory (ReRAM) based equivalence, as well as a TCAM and a BCNN accelerator based on complementary metal-oxide-semiconductor (CMOS) devices.

关键词： Ferroelectric field-effect transistor in-memory processing ternary content-addressable memory binary convolutional neural network

来源：评论

学校读者我要写书评

暂无评论

An Overview of in-memory processing with Emerging Non-volatile memory for Data-intensive Applications 19

An Overview of In-memory Processing with Emerging Non-volati...

引用

29th Great Lakes Symposium on VLSI (GLSVLSI)

作者： Li, Bing Yan, Bonan Li, Hai Helen Duke Univ ECE Dept Durham NC 27708 USA US Army Res Off Res Triangle Pk NC 27709 USA

ISBN: (纸本)9781450362528

The conventional von Neumann architecture has been revealed as a major performance and energy bottleneck for rising data-intensive applications. The decade-old idea of leveraging in-memory processing to eliminate substantial data movements has returned and led extensive research activities. The effectiveness of in-memory processing heavily relies on the memory scalability, which cannot be satisfied by traditional memory technologies. Emerging non-volatile memories (eNVMs) that pose appealing qualities such as excellent scaling and low energy consumption, on the other hand, have been heavily investigated and explored for realizing in-memory processing architecture. In this paper, we summarize the recent research progress in eNVM-based in-memory processing from various aspects, including the adopted memory technologies, locations of the in-memory processing in system, supported arithmetics, as well as applied applications.

关键词： Data-intensive applications emerging non-volatile memory in-memory processing

来源：评论

学校读者我要写书评

暂无评论

Highly Parallel Regular Expression Matching Using a Real processing-in-memory System

引用

IEEE ACCESS 2025年 13卷 18937-18951页

作者： Joo, Jeonghyeon Kim, Hyojune Han, Hyuck Im, Eul Gyu Kang, Sooyong Hanyang Univ Dept Comp Sci Seoul 04763 South Korea Dongduk Womens Univ Dept Comp Sci Seoul 02748 South Korea

processing-in-memory (PIM) is an emerging computing paradigm exploiting a cutting-edge memory device (PIM device) that integrates hundreds to thousands of processing units with the memory modules. A data-intensive application running in a host system can offload a portion of its tasks to the processing units in the PIM device, not only to exploit their processing capabilities but also to mitigate the contention in host memory accesses. However, such task offloading has the intrinsic overhead of transferring data between host memory and PIM device, which frequently hinders obtaining performance gain by exploiting the device. In this paper, we present a framework for a PIM-enabled regular expression matching that offloads the pattern-matching (scanning) engine to the PIM device, taking care to minimize the overhead. We implement an application based on the framework that runs on an off-the-shelf PIM system that has recently emerged into the market, and investigate the feasibility of processing-in-memory by comparing its performance with its PIM-oblivious implementation. Experimental results on a real system show that our application reduces the overall execution time by up to 96% compared with the multithreaded PIM-oblivious application when the input data size is 1 GB.

关键词： Random access memory Central processing Unit memory modules Data transfer Instruction sets In-memory computing Parallel processing Resource management Process control Performance evaluation processing-in-memory in-memory processing regular expression matching

来源：评论

学校读者我要写书评

暂无评论

Liquid Silicon: A Nonvolatile Fully Programmable processing-in-memory Processor With Monolithically Integrated ReRAM

引用

IEEE JOURNAL OF SOLID-STATE CIRCUITS 2020年第4期55卷 908-919页

作者： Zha, Yue Nowak, Etienne Li, Jing Univ Penn Dept Elect & Syst Engn Philadelphia PA 19104 USA CEA Leti Minatec Campus F-38054 Grenoble France

The slowdown of the CMOS technology scaling, and the trade-off between efficiency and flexibility have fueled the exploration into novel architectures with emerging post-CMOS technology [e.g., resistive-RAM (RRAM)]. In this article, a nonvolatile fully programmable processing-in-memory (PIM) processor named Liquid Silicon is demonstrated, which combines the superior programmability of general-purpose computing devices [e.g., field-programmable gate array (FPGA)] and the high efficiency of domain-specific accelerators. Besides the general computing applications, Liquid Silicon is particularly well suited for artificial intelligence (AI)/machine learning and big data applications, which not only poses high computational/memory demand but also evolves rapidly. To fabricate the Liquid Silicon chip, the HfO2 RRAM is monolithically integrated on top of the commercial 130 nm CMOS. Our measurement confirms that Liquid Silicon chip can operate reliably at a low voltage of 650 mV. It achieves 60.9 TOPS/W in performing neural network (NN) inferences, and 480 GOPS/W in performing content-based similarity search (a key big data application) at a nominal voltage supply of 1.2 V, showing $3\times $ and $100\times $ improvement over the state-of-the-art domain-specific CMOS-/RRAM-based accelerators. In addition, it outperforms the latest nonvolatile FPGA in energy efficiency by $3\times $ in general computing applications.

关键词： in-memory processing neural network (NN) nonvolatile reconfigurable architecture resistive-RAM (RRAM) ternary content-addressable memory

来源：评论

学校读者我要写书评

暂无评论

Silent-PIM: Realizing the processing-in-memory Computing With Standard memory Requests

引用

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2022年第2期33卷 251-262页

作者： Kim, Chang Hyun Lee, Won Jun Paik, Yoonah Kwon, Kiyong Kim, Seok Young Park, Il Kim, Seon Wook Korea Univ Dept Elect Engn Seoul 02841 South Korea K Hynix Inc Icheon 467866 South Korea

The Deep Neural Network (DNN), Recurrent Neural Network (RNN) applications, rapidly becoming attractive to the market, process a large amount of low-locality data;thus, the memory bandwidth limits their peak performance. Therefore, many data centers actively adapt high-bandwidth memory like HBM2/HBM2E to resolve the problem. However, this approach would not provide a complete solution since it still transfers the data from the memory to the computing unit. Thus, processing-in-memory (PIM), which performs the computation inside memory, has attracted attention. However, most previous methods require the modification or the extension of core pipelines and memory system components like memory controllers, making the practical implementation of PIM very challenging and expensive in development. In this article, we propose a Silent-PIM that performs the PIM computation with standard DRAM memory requests;thus, requiring no hardware modifications and allowing the PIM memory device to perform the computation while servicing non-PIM applications' memory requests. We can achieve our design goal by preserving the standard memory request behaviors and satisfying the DRAM standard timing requirements. In addition, using standard memory requests makes it possible to use DMA as a PIM's offloading engine, resulting in processing the PIM memory requests fast and making a core perform other tasks. We compared the performance of three Long Short-Term memory models (LSTM) kernels on real platforms, such as the Silent-PIM modeled on the FPGA, GPU, and CPU. For (p x 512) x (512 x 2048) matrix multiplication with a batch size p varying from 1 to 128, the Silent-PIM performed up to 16.9x and 24.6x faster than GPU and CPU, respectively, p = 1, which was the case without having any data reuse. At p = 128, the highest data reuse case, the GPU performance was the highest, but the PIM performance was still higher than the CPU execution. Similarly, at (p x 2048) element-wise multiplication and ad

关键词： Silent-PIM in-memory processing standard memory requests DMA LSTM

来源：评论

学校读者我要写书评

暂无评论

Z-PIM: A Sparsity-Aware processing-in-memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks

引用

IEEE JOURNAL OF SOLID-STATE CIRCUITS 2021年第4期56卷 1093-1104页

作者： Kim, Ji-Hoon Lee, Juhyoung Lee, Jinsu Heo, Jaehoon Kim, Joo-Young Korea Adv Inst Sci & Technol Dept Elect Engn Daejeon 34141 South Korea

We present an energy-efficient processing-in-memory (PIM) architecture named Z-PIM that supports both sparsity handling and fully variable bit-precision in weight data for energy-efficient deep neural networks. Z-PIM adopts the bit-serial arithmetic that performs a multiplication bit-by-bit through multiple cycles to reduce the complexity of the operation in a single cycle and to provide flexibility in bit-precision. To this end, it employs a zero-skipping convolution SRAM, which performs in-memory AND operations based on custom 8T-SRAM cells and channel-wise accumulations, and a diagonal accumulation SRAM that performs bit- and spatial-wise accumulation on the channel-wise accumulation results using diagonal logic and adders to produce the final convolution outputs. We propose the hierarchical bitline structure for energy-efficient weight bit pre-charging and computational readout by reducing the parasitic capacitances of the bitlines. Its charge reuse scheme reduces the switching rate by 95.42x0025;for the convolution layers of VGG-16 model. In addition, Z-PIMx2019;s channel-wise data mapping enables sparsity handling by skip-reading the input channels with zero weight. Its read-operation pipelining enabled by a read-sequence scheduling improves the throughput by 66.1x0025;. The Z-PIM chip is fabricated in a 65-nm CMOS process on a 7.568-mm(2) die, while it consumes average 5.294-mW power at 1.0-V voltage and 200-MHz frequency. It achieves 0.31x2013;49.12-TOPS/W energy efficiency for convolution operations as the weight sparsity and bit-precision vary from 0.1 to 0.9 and 1 to 16 bit, respectively. For the figure of merit considering input bit-width, weight bit-width, and energy efficiency, the Z-PIM shows more than 2.1 times improvement over the state-of-the-art PIM implementations.

关键词： Computer architecture Random access memory Convolution Computational modeling memory management Neural networks Bandwidth Architecture bit-scalability bit-serial operation deep learning (DL) deep neural network (DNN) energy-efficient SRAM hierarchical bitline in-memory processing near-memory processing non-von Neumann architecture processing-in-memory (PIM) architecture sparsity aware SRAM

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：