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Process-Variation-Aware in-memory computation With Improved Linearity Using On-Chip Configurable Current-Steering Thermometric DAC

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第10期71卷 4586-4596页

作者： Saragada, Prasanna Kumar Das, Bishnu Prasad Indian Inst Technol Roorkee IIT Roorkee Dept Elect & Commun Engn Roorkee 247667 Uttarakhand India STMicrolectronics Noida 201308 India

The in-memory computation (IMC) is a potentialtechnique to improve the speed and energy efficiency of data-intensive designs. However, the scalability of IMC to largesystems is hindered by the non-linearities of analog multiply-and-accumulate (MAC) operations and process variation, whichimpacts the precision of high bit-width MAC operations. In thispaper, we present an IMC architecture that is capable of perform-ing multi-bit MAC operations with improved speed, linearity, andcomputational accuracy. To improve the speed/linearity of theIMC-MAC operations, the image and weight data are applied byusing the pulse amplitude modulation (PAM) and thermometrictechniques, respectively. Although the PAM technique improvesthe speed of the IMC-MAC operations, it has linearity issuesthat need to be addressed. Based on the detailed linearity analysisof the IMC-MAC circuit, we proposed two approaches to improvethe linearity and the signal margin (SM) of the IMC *** proposed configurable current steering thermometric digital-to-analog converter (CST-DAC) array is employed to provide thePAM signals with various dynamic ranges and non-linear gapsthat are required to improve the linearity/SM. The proposedcombined PAM and thermometric IMC (PT-IMC) architectureis designed and fabricated in the TSMC 180-nm CMOS *** post-silicon calibration of the design point mitigates theprocess-variation issues and provides the maximum SM (closeto the simulation results). Furthermore, the proposed PT-IMCarchitecture performs MNIST/CIFAR-10 data set classificationwith an accuracy of 98%/88%. In addition, the PT-IMC archi-tecture achieves a peak throughput of 12.41 GOPS, a normalizedenergy efficiency of 30.64 TOPS/W, a normalized figure-of-merit(FOM) of 3039, a loss in the SM of 8.3% with respect to theideal SM, and a computational error of 0.41%

关键词： Computer architecture Linearity Discharges (electric) Codes Arrays Voltage SRAM cells computation using analog signals in-memory computation multiply-and-accumulate (MAC) operation machine learning classifier on-chip calibration

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Translation of Array Expressions for in-memory computation on Memristive Crossbar 36

Translation of Array Expressions for In-Memory Computation o...

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36th International Conference on VLSI Design (VLSID) / 22nd International Conference on Embedded Systems (ES)

作者： Pyne, Sumanta Natl Inst Technol Rourkela Dept Comp Sci & Engn Sundargarh 769008 Odisha India

ISBN: (纸本)9798350346787

The von Neumann architectures have a bottleneck of data transfer between memory and processing unit. This degrades performance and increases power consumption for data-intensive applications. The advent of memristor based logic in recent times has provided the opportunities to design non-von Neumann architectures capable of performing computation within the memory. The universal NOR logic gate can be realized on a memristor based crossbar memory array. This allow complex arithmetic and logic operations within the memory. This paper proposes a code generation technique for in-memory computation of array expressions in a program written in high level language. An instruction set for in-memory computation has been considered. Space is allocated for array elements, temporary variables for intermediate results and memory isolation gaps for parallel operations. A sequence of NOR/NOT operations is generated to enable in-memory computation of array expressions. An evaluation is done on eight benchmark programs. in-memory computation without memory isolation achieves energy savings by an average of 35% at the cost of 44% average performance degradation. in-memory computation with memory isolation achieves energy savings by an average of 29% at the cost of 25% average performance degradation.

关键词： Memristor crossbar array in-memory computation array operation translation

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Enabling Novel in-memory computation Algorithms to Address Next-Generation Throughput Constraints on SWaP-Limited Platforms

Enabling Novel In-Memory Computation Algorithms to Address N...

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IEEE High Performance Extreme Computing Virtual Conference (HPEC)

作者： Ray, Jessica Meiners, Chad R. MIT Lincoln Lab Lexington MA USA

ISBN: (数字)9781665497862

ISBN: (纸本)9781665497862

The Department of Defense relies heavily on filtering and selection applications to help manage the overwhelming amount of data constantly received at the tactical edge. Filtering and selection are both latency and throughput constrained, and systems at the tactical edge must heavily optimize their SWaP (size, weight, and power) usage, which can reduce overall computation and memory performance. in-memory computation (IMC) provides a promising solution to the latency and throughput issues, as it helps enable the efficient processing of data as it is received, helping eliminate the memory bottleneck imposed by traditional Von Neumann architectures. In this paper, we discuss a specific type of IMC accelerator known as a Content Addressable memory (CAM), which effectively operates as a hardware-based associative array, allowing fast lookup and match operations. In particular, we consider ternary CAMs (TCAMs) and their use within string matching, which are an important component of many filtering and selection applications. Despite the benefits gained with TCAMs, designing applications that utilize them remains a difficult task. Straightforward questions, such as "how large should my TCAM be?" and "what is the expected throughput?" are difficult to answer due to the many factors that go into effectively mapping data into a TCAM. This work aims to help answer these types of questions with a new framework called Stardust-Chicken. Stardust-Chicken supports generating and simulating TCAMs, and implements state-of-the-art algorithms and data representations that can effectively map data into TCAMs. With Stardust-Chicken, users can explore the tradeoff space that comes with TCAMs and better understand how to utilize them in their applications.

关键词： in-memory computation content addressable memory string matching

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A Novel Scalable Kernelized Fuzzy Clustering Algorithms Based on in-memory computation for Handling Big Data

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IEEE TRANSACTIONS ON EMERGING TOPICS IN computationAL INTELLIGENCE 2021年第6期5卷 908-919页

作者： Jha, Preeti Tiwari, Aruna Bharill, Neha Ratnaparkhe, Milind Mounika, Mukkamalla Nagendra, Neha Indian Inst Technol Indore 453552 India Mahindra Univ Ecole Cent Sch Engn Hyderabad 500043 India ICAR Indian Inst Soybean Res Indore 452001 India

Traditional scalable clustering algorithms mainly deal with the clustering of linearly separable data, but it is challenging to cluster the non-linear separable data efficiently in the feature space. In this article, we propose a novel Kernelized Scalable Random Sampling with Iterative Optimization Fuzzy c-Means (KSRSIO-FCM) clustering algorithm using Big Data framework. To propose the KSRSIO-FCM, we also propose the Kernelized version of Scalable Literal Fuzzy c-Means (KSLFCM) clustering algorithm, which is an integral part of the proposed KSRSIO-FCM algorithm. These kernelized clustering algorithms are evolved to deal with the non-linear separable problems by applying a kernel Radial Basis Functions (RBF) which maps the input data space non-linearly into a high dimensional feature space. We aim to design and implement the kernelized fuzzy clustering algorithms on Apache Spark, which performs the efficient clustering of Big Data due to its in-memory cluster computing technique. Exhaustive experiments are performed on various big datasets to show the effectiveness of proposed KSRSIO-FCM in comparison with other scalable clustering algorithms, i.e., KSLFCM, SRSIO-FCM, and SLFCM. The reported experimental results show that the KSRSIO-FCM algorithm in comparison with KSLFCM, SRSIO-FCM, and SLFCM achieves significant improvement in terms of time and space complexity, Normalized Mutual Information (NMI), Adjusted Rand Index (ARI), and F-score, respectively. Furthermore, we have carried out a performance analysis of KSRSIO-FCM versus KSLFCM. Thus, the reported results show that the KSRSIO-FCM implemented on Apache Spark has better potential for Big Data clustering as compared to traditional scalable fuzzy clustering methods.

关键词： Clustering algorithms Kernel Big Data Optimization Kernelized clustering algorithms Big Data Nonlinear separable in-memory computation

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Trends and Opportunities for SRAM Based In-memory and Near-memory computation 22

Trends and Opportunities for SRAM Based In-Memory and Near-M...

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22nd International Symposium on Quality Electronic Design (ISQED)

作者： Srinivasa, Srivatsa Ramanathan, Akshay Krishna Sundaram, Jainaveen Kurian, Dileep Gopal, Srinivasan Jain, Nilesh Srinivasan, Anuradha Iyer, Ravi Narayanan, Vijaykrishnan Karnik, Tanay Intel Corp Santa Clara CA 95051 USA Penn State Univ University Pk PA 16802 USA

ISBN: (纸本)9781728176413

Changes in application trends along with increasing number of connected devices have led to explosion in the amount of data being generated every single day. Computing systems need to efficiently process these huge amounts of data and generate results, classify objects, stream high quality videos and so on. In-memory Computing and Near-memory Computing have been emerged as the popular design choices to address the challenges in executing the above-mentioned tasks. Through In-memory Computing, SRAM Banks can be repurposed as compute engines while performing Bulk Boolean operations. Near-memory techniques have shown promise in improving the performance of Machine learning tasks. By carefully understanding the design we describe the opportunities towards amalgamating both these design techniques for obtaining further performance enhancement and achieving lower power budget while executing fundamental Machine Learning primitives. In this work, we take the example of Sparse Matrix Multiplication, and design an I-NMC accelerator which speeds up the index handling by 10x-60x and 10x-70x energy efficiency based on the workload dimensions as compared with non I-NMC solution occupying just 1% of the overall hardware area.

关键词： in-memory computation Near-memory computation SRAM

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A Logic Compatible 4T Dual Embedded DRAM Array for in-memory computation of Deep Neural Networks

A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory...

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IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

作者： Yoo, Taegeun Kim, Hyunjoon Chen, Qian Kim, Tony Tae-Hyoung Kim, Bongjin Nanyang Technol Univ Sch Elect & Elect Engn 50 Nanyang Ave Singapore 639798 Singapore

ISBN: (纸本)9781728129549

Modern deep neural network (DNN) systems evolved under the ever-increasing demands of handling more complex and computation-heavy tasks. Traditional hardware designed for such tasks had larger size memory and power consumption issue due to extensive on/off-chip memory access. In-memory computing, one of the promising solutions to resolve the issue, dramatically reduced memory access and improved energy efficiency by utilizing the memory cell to function as both a data storage and a computing element. Embedded DRAM (eDRAM) is one of the potential candidates for in-memory computation. Its minimal use of circuit components and low static power consumption provided design advantage while its relatively short retention time made eDRAM unsuitable for certain applications. This work introduces a dot-product processing macro using eDRAM array and explores its capability as an in-memory computing processing element. The proposed architecture implemented a pair of 2T eDRAM cells as a processing unit that can store and operate with ternary weights using only four transistors. Besides, we investigated a method to maximize the retention time in conjunction with analyzing the device mismatch. An input/weight bit-precision reconfigurable 4T eDRAM processing array shows the energy efficiency of 1.81fJ/OP (including refresh energy) when it operates with binary inputs and ternary weights.

关键词： in-memory computation DNN embedded DRAM analog computation hardware acceleration inference dot-product

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in-memory computation of a Machine-Learning Classifier in a Standard 6T SRAM Array

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2017年第4期52卷 915-924页

作者： Zhang, Jintao Wang, Zhuo Verma, Naveen Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

This paper presents a machine-learning classifier where computations are performed in a standard 6T SRAM array, which stores the machine-learning model. Peripheral circuits implement mixed-signal weak classifiers via columns of the SRAM, and a training algorithm enables a strong classifier through boosting and also overcomes circuit nonidealities, by combining multiple columns. A prototype 128 x 128 SRAM array, implemented in a 130-nm CMOS process, demonstrates ten-way classification of MNIST images (using image-pixel features downsampled from 28 x 28 = 784 to 9 x 9 = 81, which yields a baseline accuracy of 90%). In SRAM mode (bit-cell read/write), the prototype operates up to 300 MHz, and in classify mode, it operates at 50 MHz, generating a classification every cycle. With accuracy equivalent to a discrete SRAM/digital-MAC system, the system achieves ten-way classification at an energy of 630 pJ per decision, 113x lower than a discrete system with standard training algorithm and 13x lower than a discrete system with the proposed training algorithm.

关键词： Analog computation classification image detection in-memory computation machine learning

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A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power in-memory computation 18

A Novel Cross-point MRAM with Diode Selector Capable of High...

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14th IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

作者： Ding, Chaoxin Kang, Wang Zhang, He Zhang, Youguang Zhao, Weisheng Beihang Univ Fert Beijing Inst BDBC Sch Elect & Informat Engn Beijing 100191 Peoples R China

ISBN: (纸本)9781450358156

in-memory computation (IMC), which is capable of reducing the power consumption and bandwidth requirement resulting from the data transfer between the processing and memory units, has been considered as a promising technology to break the von-Neumann bottleneck. In order to develop an effective and efficient IMC platform, the performance, such as density, operation speed and power consumption, of the memory itself is one of the most important keys. In this work, we report a cross-point magnetic random access memory (MRAM) with diode selector for IMC implementation. The memory cell consists of a magnetic tunnel junction (MTJ) device and a diode connected in series. The memory cells are arranged in a cross-point array structure, providing high storage density. The MTJ can be switched through the unipolar precessional voltage-controlled magnetic anisotropy (VCMA) effect, thus enabling high speed and low power. Further, Boolean logic functions can be realized via regular memory-like write & read operations. The feasibility and performance of the proposed IMC in the cross-point MRAM are successfully demonstrated with hybrid VCMA-MTJ/CMOS circuit simulations under the 40 nm technology node.

关键词： Cross-point MRAM in-memory computation VCMA

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Processing Data Where It Makes Sense in Modern Computing Systems: Enabling in-memory computation 7

Processing Data Where It Makes Sense in Modern Computing Sys...

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7th Mediterranean Conference on Embedded Computing (MECO)

作者： Mutlu, Onur Swiss Fed Inst Technol Zurich Switzerland Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781538656839

Today's systems are overwhelmingly designed to move data to computation. This design choice goes directly against at least three key trends in systems that cause performance, scalability and energy bottlenecks: 1) data access from memory is already a key bottleneck as applications become more data-intensive and memory bandwidth and energy do not scale well, 2) energy consumption is a key constraint in especially mobile and server systems, 3) data movement is very expensive in terms of bandwidth, energy and latency, much more so than computation. These trends are especially severely-felt in the data-intensive server and energy-constrained mobile systems of today. At the same time, conventional memory technology is facing many scaling challenges in terms of reliability, energy, and performance [1-23]. As a result, memory system architects are open to organizing memory in different ways and making it more intelligent, at the expense of slightly higher cost. The emergence of 3D-stacked memory plus logic as well as the adoption of error correcting codes inside the latest DRAM chips are an evidence of this trend. In this talk, I will discuss some recent research that aims to practically enable computation close to data. After motivating trends in applications as well as technology, we will discuss at least two promising directions: 1) performing massively-parallel bulk operations in memory by exploiting the analog operational properties of DRAM, with low-cost changes [24-28], 2) exploiting the logic layer in 3D-stacked memory technology in various ways to accelerate important data-intensive applications [28-36]. In both approaches, we will discuss relevant cross-layer research, design, and adoption challenges in devices, architecture, systems, and programming models. Our focus will be the development of in-memory processing designs that can be adopted in real computing platforms at low cost.

关键词： in-memory computation DRAM data movement memory bottleneck

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An Adaptive Tuning Strategy on Spark Based on in-memory computation Characteristics 18

An Adaptive Tuning Strategy on Spark Based on In-memory Comp...

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18th International Conference on Advanced Communication Technology (ICACT)

作者： Zhao, Yao Hu, Fei Chen, Haopeng Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn 800 Dongchuan Rd Shanghai Peoples R China

ISBN: (纸本)9788996865063

We present an adaptive tuning method to improve Spark performance, especially for its in-memory computation. This manner serves one purpose: making a better use of memory reasonably through adaptively adopting suitable category based on Spark application runtime statistics on different working sets. This solution works in two steps. Firstly, it collects run-time statistics dynamically and stores them in round-robin structures to save memory. Secondly, it can change system storage category based on these statistics. Additionally we focus on serialization strategy optimization. For this purpose we test Spark integrated serialization algorithms: Java and Kryo serialization algorithms, and make a comparison of their performance. In order to gain flexibility we change Spark serialization mechanism by setting the default serialization unit from one RDD to one block. In this way, for the case which RDD has huge amount of blocks our solution can use different serialization algorithms to serialize different blocks in one RDD. We show that our solution is expressive enough to obtain 2x speedup than original Spark when there is inadequate memory resource.

关键词： Spark adaptive tuning in-memory computation serialization

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