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8th International Conference on Contemporary Computing (IC3)

作者： Ketu, Shwet Agarwal, Sonali Indian Inst Informat Technol Allahabad Uttar Pradesh India

ISBN: (纸本)9781467379489

Big Data analytics are recently coming up as prominent research area in the field of Information Technology serving various data driven domains for effective processing of big data. Big data analytics have been facing various challenges such as inefficient storage, processing delays, low rate of information retrieval, complex algorithms which cannot be handled and managed using traditional methods. For assisting software developers to deal with big data challenges, new programming frameworks are required. In this research paper Hadoop MapReduce and Apache Spark are taken for this purpose which supports on-disk and in-memory computation respectively. Clustering is one of the important tasks of big data mining used for information retrieval and knowledge discovery. In this research work, we are analyzing the performance of distributed K-Means clustering based on in-memory and on-disk computational models. For performance enhancement of distributed K-Means clustering, in-memory and on-disk computational models have been adopted and an experimental analysis has been performed.

关键词： Big data Big data analytic Distributed K-Mean Hadoop MapReduce Apche Spark On- disk computation in-memory computation

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PRESTO: A Processing-in-memory-Based <inline-formula><tex-math notation="LaTeX">$k$</tex-math></inline-formula>-SAT Solver Using Recurrent Stochastic Neural Network With Unsupervised Learning

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2024年第4期59卷 1204-1215页

作者： Kim, Daehyun Rahman, Nael Mizanur Mukhopadhyay, Saibal Georgia Inst Technol Dept Elect & Comp Engn Atlanta GA 30332 USA

In this article, we introduce a processing-in-memory (PIM)-based satisfiability (SAT) solver called Processing-in-memory-based SAT solver using a Recurrent Stochastic neural network (PRESTO), a mixed-signal circuit-based PIM (MSC-PIM) architecture combined with a digital finite state machine (FSM) for solving SAT problems. The presented design leverages a stochastic neural network with unsupervised learning. PRESTO's architecture supports fully connected k -SAT clauses with mixed- k problems, highlighting its versatility in handling a wide range of SAT challenges. A test chip is fabricated in 65-nm CMOS technology with a core size of 0.4 mm(2) and demonstrates an operating frequency range of 100-500 MHz and a peak power of 35.4 mW. The measurement results show that PRESTO achieves a 74.0% accuracy for three-SAT problems with 30 variables and 126 clauses.

关键词： Boolean satisfiability (SAT) problem in-memory computation on-chip learning stochastic neural network unsupervised learning

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eDRAM-CIM: Reconfigurable Charge Domain Compute-In-memory Design With Embedded Dynamic Random Access memory Array Realizing Adaptive Data Converters

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2024年第6期59卷 1950-1961页

作者： Xie, Shanshan Ni, Can Sayal, Aseem Jain, Pulkit Hamzaoglu, Fatih Kulkarni, Jaydeep P. Univ Texas Austin Dept Elect & Comp Engn Austin TX 78712 USA Google LLC Sunnyvale CA 94089 USA Intel Circuit Res Lab Hillsboro OR 97124 USA

This article presents a compute-in-memory (CIM) architecture for a large-scale machine learning (ML) accelerator, which employs 1T1C embedded dynamic random access memory (eDRAM) bitcells as charge domain circuits for convolution neural network (CNN) multiply-accumulation-averaging (MAV) computations. By repurposing existing 1T1C eDRAM columns to construct an adaptive data converter, dot-product, averaging, pooling, and rectified linear unit (ReLU) activation on the memory array, the eDRAM-CIM design eliminates the need for an extra dedicated hardware accelerator, which significantly reduces the hardware implementation cost and increases the reconfigurability of the CIM computation circuit. In the eDRAM-CIM design, 8 b digital inputs from image pixel values are converted to analog domain directly on eDRAM columns. The dot-product is computed without disturbing the kernel weights, which are stored in the eDRAM array, preventing data duplication and additional intra-memory data movement. In addition, the convolution results are transferred back to the digital domain using an in-eDRAM adaptive dynamic range successive-approximation (SAR) analog-to-digital converter (ADC) utilizing a narrow range of dot-product distribution to reduce ADC latency and energy. A 16 Kb eDRAM-CIM prototype, implemented in the 65 nm CMOS process, demonstrates the concept and the functionality of the test-chip using the CIFAR-10 dataset with 8 b input and 8 b signed weight, achieving 90.77% accuracy, 4.71 GOPS throughput, 4.76 TOPS/W energy efficiency, and 8.26 GOPS/mm(2). A scalability analysis is developed to show that the presented eDRAM-CIM approach, which was adopted in an advanced eDRAM technology node, shows promising energy efficiency (11.21 TOPS/W) and throughput (22.2 TOPS), suggesting its potential for application in large-scale energy-efficient CIM designs.

关键词： Analog computation compute-in-memory (CIM) dot-product embedded dynamic random access memory (eDRAM) in-memory computation machine learning (ML) ML accelerator

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PERFORMANCE COMPARISON OF APACHE SPARK AND HADOOP FOR MACHINE LEARNING BASED ITERATIVE GBTR ON HIGGS AND COVID-19 DATASETS

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SCALABLE COMPUTING-PRACTICE AND EXPERIENCE 2024年第3期25卷 1373-1386页

作者： Sewal, Piyush Singh, Hari Jaypee Univ Informat Technol CSE & IT Dept Solan HP India

In the realm of distributed computing frameworks, such as Apache Spark and MapReduce Hadoop, the efficacy of these frameworks varies across diverse applications and algorithms contingent upon distinctive evaluation metrics and critical parameters. This research paper diligently scrutinizes the extant body of research that compares these two frameworks concerning said evaluation metrics and parameters. Subsequently, it conducts empirical investigations to authenticate the performance of these frameworks in the context of an iterative Gradient Boosting Tree Regression (GBTR) algorithm. Remarkably, the comparative analyses in previous studies encompass a spectrum of iterative machine learning regression and classification techniques, batch processing, SQL, and Graph processing algorithms. Furthermore, numerous investigations have explored the application of machine learning algorithms encompassing logistic regression, Page Rank, K -Means, KNN, and the HiBench suite. This paper presents the comparison between the two distributed computing platforms on iterative GBTR for classification task on the HIGGS dataset from the physics domain and for the regression task on the Covid-19 dataset from the healthcare domain. The empirical findings corroborate that Apache Spark exhibits superior execution speed in iterative tasks when the available physical memory significantly exceeds the dataset size. Conversely, Hadoop outperforms Spark when dealing with substantial datasets or constrained physical memory resources.

关键词： MapReduce Hadoop Spark Machine Learning Iterative in-memory computation Gradient Boost Tree Regres- sion Covid-19

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New Zero Power Memristor Emulator Model and Its Application in Memristive Neural computation

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IEEE ACCESS 2023年 11卷 5609-5616页

作者： Kumar, Prashant Srivastava, Pushkar Ranjan, Rajeev Kumar Kumngern, Montree Indian Inst Technol ISM Dept Elect Engn Dhanbad 826004 Jharkhand India King Mongkuts Inst Technol Ladkrabang Sch Engn Dept Telecommun Engn Bangkok 10520 Thailand

We present here a simple three P-type MOSFET-based grounded memristor emulator model. The model is designed to achieve zero static power dissipation and is done so by eliminating the external DC supply i.e., no DC bias. The proposed memristor emulator model has extremely low dynamic power dissipation as well which comes to around 175 nW i.e., similar to 67% improvement compared to recent work. A mathematical analysis is carried out to present the relevance of this design. Simulations were done on Cadence Virtuoso 90 nm technology node and fingerprints of the proposed memristor emulator were obtained. The layout area occupied by the model is approx 1154.69 mu m(2) and an external capacitor is connected to add tunability to the circuit. Furthermore, Monte Carlo and corner analysis validate the robust nature of the design. Besides, simulations have been experimentally verified using CD-4007 CMOS integrated circuit (IC) to make the design practically feasible. Furthermore, the design offers advantages such as extremely less overall power consumption and smaller chip area that could possibly pave the path for fabrication using standard CMOS technologies. At last, an application of the proposed model depicting in-memory computation through a memristor emulator crossbar array is presented in brief.

关键词： Memristors Integrated circuit modeling Mathematical models Capacitors Transistors Power demand Semiconductor device modeling CMOS integrated circuits Monte Carlo methods Memristor emulator CMOS pinched hysteresis loop (PHL) Monte Carlo in-memory computation

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Assessing the Effectiveness of Non-Turing Computing Paradigms

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IEEE ACCESS 2023年 11卷 98751-98763页

作者： Rocutto, Lorenzo Maronese, Marco Traversa, Fabio Lorenzo Decherchi, Sergio Cavalli, Andrea Fdn Ist Italiano Tecnol Comp & Chem Biol I-16163 Genoa Italy Univ Bologna Dept Pharm & Biotechnol I-40126 Bologna Italy Memcomputing Inc San Diego CA 92121 USA Fdn Ist Italiano Tecnol Data Sci & Comp I-16163 Genoa Italy

In recent years the technological limits inherently present in the classical Turing paradigm of computation have sparked the development of innovative solutions based on quantum devices or analog-digital mixed approaches often based on the time evolution of differential equations. Such promising machinery require accurate analysis to understand if and howthey will be able to perform better than classical approaches in solving hard optimization problems. Here we challenge two machines representative of the quantum annealing and differential equations approaches, namely D-Wave and Memcomputing by devising a benchmark of three well known hard optimization problems from the realms of number theory, optimal transport and optimal scheduling. We introduce the Mean First Solution Time, a novel metric for accurately comparing performances, and take as baseline the classical Gurobi solver. We show that performances of both solvers are heavily dependent on the selected set of internal parameters. Results shed lights on the advantages and current limits of each paradigm and give a perspective on possible future developments.

关键词： Factorization problem in-memory computation non-linear dynamical systems non-turing computation NP optimization problems optimal transport quantum annealing.

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CONV-SRAM: An Energy-Efficient SRAM With In-memory Dot-Product computation for Low-Power Convolutional Neural Networks

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2019年第1期54卷 217-230页

作者： Biswas, Avishek Chandrakasan, Anantha P. Texas Instruments Inc Kilby Labs Dallas TX 75243 USA MIT Dept Elect Engn & Comp Sci Cambridge MA 02139 USA

This paper presents an energy-efficient static random access memory (SRAM) with embedded dot-product computation capability, for binary-weight convolutional neural networks. A 10T bit-cell-based SRAM array is used to store the 1-b filter weights. The array implements dot-product as a weighted average of the bitline voltages, which are proportional to the digital input values. Local integrating analogto- digital converters compute the digital convolution outputs, corresponding to each filter. We have successfully demonstrated functionality (> 98% accuracy) with the 10 000 test images in the MNIST hand-written digit recognition data set, using 6-b inputs/outputs. Compared to conventional full-digital implementations using small bitwidths, we achieve similar or better energy efficiency, by reducing data transfer, due to the highly parallel in-memory analog computations.

关键词： Analog computing binary weights convolutional neural networks (CNNs) dot-product edge-computing energy-efficient SRAM in-memory computation machine learning (ML)

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Energy Efficient Logic and memory Design With Beyond-CMOS Magnetoelectric Spin-Orbit (MESO) Technology Toward Ultralow Supply Voltage

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IEEE JOURNAL ON EXPLORATORY SOLID-STATE computationAL DEVICES AND CIRCUITS 2023年第2期9卷 124-133页

作者： Rothe, Rohit Li, Hai Nikonov, Dmitri E. Young, Ian A. Choo, Kyojin Blaauw, David Univ Michigan Dept Elect & Comp Engn Ann Arbor MI 48105 USA Intel Corp Components Res Grp Hillsboro OR 97124 USA Swiss Fed Inst Technol Lausanne EPFL CH-1015 Lausanne Switzerland

Devices based on the spin as the fundamental computing unit provide a promising beyond-complementary metal-oxide-semiconductor (CMOS) device option, thanks to their energy efficiency and compatibility with CMOS. One such option is a magnetoelectric spin-orbit (MESO) device, an attojoule-class emerging technology promising to extend Moore's law. This article presents circuit design and optimization techniques, such as device stacking and a canary circuit-based asynchronous clock pulse generation scheme for MESO device technology. With these targeted circuit techniques, the MESO energy efficiency can be improved by similar to 1.5 x. Novel architectures for arithmetic logic and effective realization of in-memory computing are also proposed that utilize the unique properties of this promising new technology.

关键词： Beyond-complementary metal-oxide-semiconductor (CMOS) logic canary circuits in-memory computation magnetoelectric (ME) SPICE spin-orbit (SO)

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NURODE: In-memory Crossbar Core for Hodgkin-Huxley Model ODE-Based computations

NURODE: In-Memory Crossbar Core for Hodgkin-Huxley Model ODE...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Gong, Andy Azghadi, Mostafa Rahimi Genov, Roman Amirsoleimani, Amirali Univ Toronto Div Engn Sci Toronto ON Canada James Cook Univ Sch Engn Townsville Qld Australia Univ Toronto Dept Elect & Comp Engn Toronto ON Canada York Univ Dept Elect Engn & Comp Sci Toronto ON Canada

ISBN: (纸本)9798350330991;9798350331004

In this work, we present a memristor crossbar array-based hardware architecture designed to solve a system of differential equations for the Hodgkin-Huxley neuron model. The system extends from previous works to perform more computations in-memory, reducing the load of software processing and distributing them onto memristive hardware along with cheap shift-and-add operations. We demonstrate the properties of the solutions produced by the system follow the expected behaviours of the Hodgkin-Huxley model under various external currents.

关键词： Memristor Crossbar in-memory computation Stochasticity Stochastic Differential Equation Vector-Matrix Multiplication Hodgkin-Huxley

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In-memory Machine Learning using Adaptive Multivariate Decision Trees and Memristors

In-memory Machine Learning using Adaptive Multivariate Decis...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Chavan, Akash Sinha, Pranav Raj, Sunny Oakland Univ Dept Comp Sci & Engn Rochester MI 48309 USA

ISBN: (纸本)9798350330991;9798350331004

We introduce a framework to design in-memory decision tree machine-learning (ML) circuits using memristor crossbars. Decision trees (DTs) offer many advantages over neural networks, such as enhanced energy efficiency, interpretability, safety, privacy, and speed, along with reduced dependence on extensive training data. We propose an adaptive multivariate decision tree (AMDT) training algorithm, which constructs decision trees that incorporate both univariate and multivariate features, facilitating the creation of higher accuracy and energy-efficient crossbar designs compared to the state-of-the-art (SOTA). Our circuits are realized using pure memristor crossbars, requiring just one memristor per cell and no transistors while employing sneak-paths for flow-based in-memory computations. In comparison to the SOTA, our approach produces designs that are, on average, 4% more accurate and require 12.6% lower energy.

关键词： in-memory computation memristors flow-based computing decision trees multivariate decision trees energy-efficient hardware

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