检索结果-内蒙古大学图书馆

Development of in-memory computing Device Using Positive Feedback Field Effect Transistor Based on NAND Flash Array

IEEE ACCESS 2025年 13卷 45449-45457页

作者： Jeong, Hangwook Park, Minseon Kwon, Min-Woo Gangneung Wonju Natl Univ Dept Elect & Semicond Engn Kangnung 25457 South Korea Seoul Natl Univ Sci & Technol Dept Elect Engn Seoul 01811 South Korea

In this study, we propose a feedback field effect transistor (FBFET) in-memory computing device based on the string of NAND flash array. By combining the polysilicon-blocking oxide-silicon nitride-tunneling oxide-silicon (SONOS) cell structure and N+-P--N--P+ body doping structure of FBFET, the device is designed in a string structure. Our in-memory computing FBFET can perform Boolean logical operations by utilizing the threshold voltage modulation characteristics of the FBFET by adjusting the control gate voltage. Additionally, we present optimized hot carrier injection conditions tailored for the in-memory computing FBFET, enabling the successful writing of results for Boolean logic operations: OR, AND, NOR, NAND. These findings contribute a novel mechanism and direction for the field of in-memory computing research.

关键词： in-memory computing Logic gates Threshold voltage Programming Logic Voltage control Flash memories Electrons Electron traps Silicon Feedback field effect transistor in-memory computing NAND flash Boolean logical operation hot carrier injection

来源：评论

学校读者我要写书评

暂无评论

Emerging 2D Ferroelectric Devices for In-Sensor and in-memory computing

引用

ADVANCED MATERIALS 2025年第2期37卷 e2400332页

作者： Chen, Chunsheng Zhou, Yaoqiang Tong, Lei Pang, Yue Xu, Jianbin Chinese Univ Hong Kong Dept Elect Engn & Mat Sci Hong Kong Peoples R China Chinese Univ Hong Kong Technol Res Ctr Hong Kong Peoples R China

The quantity of sensor nodes within current computing systems is rapidly increasing in tandem with the sensing data. The presence of a bottleneck in data transmission between the sensors, computing, and memory units obstructs the system's efficiency and speed. To minimize the latency of data transmission between units, novel in-memory and in-sensor computing architectures are proposed as alternatives to the conventional von Neumann architecture, aiming for data-intensive sensing and computing applications. The integration of 2D materials and 2D ferroelectric materials has been expected to build these novel sensing and computing architectures due to the dangling-bond-free surface, ultra-fast polarization flipping, and ultra-low power consumption of the 2D ferroelectrics. Here, the recent progress of 2D ferroelectric devices for in-sensing and in-memory neuromorphic computing is reviewed. Experimental and theoretical progresses on 2D ferroelectric devices, including passive ferroelectrics-integrated 2D devices and active ferroelectrics-integrated 2D devices, are reviewed followed by the integration of perception, memory, and computing application. Notably, 2D ferroelectric devices have been used to simulate synaptic weights, neuronal model functions, and neural networks for image processing. As an emerging device configuration, 2D ferroelectric devices have the potential to expand into the sensor-memory and computing integration application field, leading to new possibilities for modern electronics. This work reviews the recent progress of 2D ferroelectric devices for in-sensing and in-memory neuromorphic computing. Experimental and theoretical progresses on 2D ferroelectric devices, including passive ferroelectrics-integrated 2D devices and active ferroelectrics-integrated 2D devices are reviewed followed by the integration of perception, memory, and computing application. Notably, the 2D ferroelectric devices have been used to simulate synaptic weights, neuronal mod

关键词： 2D materials ferroelectric device in-memory computing in-sensor computing neural network

来源：评论

学校读者我要写书评

暂无评论

Analysis of Low Area Digital Up/Down Clipping Counter for Digital in-memory computing

引用

IEEE ACCESS 2025年 13卷 32808-32818页

作者： Lee, Siyeol Lee, Geonwoo Ahn, Seongmin Na, Taehui Incheon Natl Univ Dept Elect Engn Incheon 22012 South Korea

As deep learning becomes more prevalent in state-of-the-art research, its energy overhead caused by the extensive data transfer has become a significant challenge. To address this issue, in-memory computing (IMC) has been actively explored as a solution, enabling computations to be performed directly within memory. Among various IMC architectures, magnetic random access memory-based digital IMC architecture for ternary output binary neural networks has garnered attention due to its ability to reduce area by utilizing a single bit-cell per synapse and guarantee accuracy through digital operation using XNOR-like operations on ternary outputs. Because a counter must be attached to each column to accumulate sum values in digital IMC macro, minimizing the area overhead of the counter is important. This paper discusses and compares the design of Up/Down Clipping Counters based on toggle flip-flop (TFF) and ripple carry adder (RCA). Finally, it proposes a novel RCA-based counter. The proposed counter achieves a 45.32% reduction in layout area compared to the TFF(J)-based AND-OR Counter which had the least modified structure from the conventional counter, resulting in a significant area reduction. Additionally, it achieves a 56.94% reduction in energy consumption.

关键词： Logic gates Computer architecture Logic Accuracy Flip-flops Main-secondary Layout Energy consumption Latches Adders Area efficient D flip-flop deep learning digital up/down counter full adder in-memory computing JK flip-flop multiplexer MRAM ripple carry adder toggle flip-flop

来源：评论

学校读者我要写书评

暂无评论

The Effect of Heavy-Ion Single Events on the Accuracy of SONOS Analog in-memory computing Accelerators

引用

IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第4期72卷 1452-1459页

作者： Wilson, Donald Dempsey, Ryan C. Xiao, T. Patrick Spear, Matthew E. Hughart, David R. Bennett, Christopher H. Agrawal, Vineet Puchner, Helmut Agarwal, Sapan Marinella, Matthew J. Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85281 USA Sandia Natl Labs Albuquerque NM 87185 USA Infineon Technol San Jose CA 95134 USA

Silicon-oxide-nitride-oxide-silicon (SONOS) charge-trap memory is a promising nonvolatile memory (NVM) device for analog in-memory computing (AIMC) applications. The sensitivity of 40-nm SONOS analog states in response to single-event effects (SEEs) was experimentally assessed by exposing an SONOS array to heavy ions with the linear energy transfers (LETs) of 28.6, 44.9, and 59.5 MeV/(mg/cm(2)). A statistical model of SEE was developed using specific criteria to distinguish them from effects unrelated to radiation, such as device-to-device programming variation, read noise, and drift. This model was used to simulate the effects of heavy ions on an AIMC accelerator processing standard deep neural networks (DNNs) running inference on common datasets, including ImageNet. Simulated inference accuracy decreases with increasing LET and fluence. At the highest LET of 59.5 MeV/(mg/cm(2)), an accuracy degradation of 5% on ImageNet was predicted at a fluence of 3 x 10(6) ions/cm(2), indicating a sufficient performance for most space applications.

关键词： SONOS devices Ions Accuracy Nonvolatile memory Ion accelerators Phase change random access memory Particle measurements Laboratories in-memory computing Atmospheric measurements Analog accelerator charge-trap memory silicon-oxide-nitride-oxide-silicon (SONOS) flash memory heavy-ion irradiation neural networks single-event effects (SEEs) single-event upset

来源：评论

学校读者我要写书评

暂无评论

Implementation of monolithic 3D integrated TiOx memristor-based neural network for high-performance in-memory computing

引用

NANO ENERGY 2025年 139卷

作者： An, Yeon Seo Kim, Dowon Park, Young Ran Eo, Jung Sun Kim, Mingyu Kim, Donghyeok Bin Kim, Hyeon Lee, Byunggeun Wang, Gunuk Korea Univ Grad Sch Converging Sci & Technol KU KIST 145 Anam Ro Seoul 02841 South Korea Gwangju Inst Sci & Technol Sch Elect Engn & Comp Sci 123 Cheomdangwagi ro Gwangju 61005 South Korea Korea Univ Dept Integrat Energy Engn 145 Anam Ro Seoul 02841 South Korea

The monolithic three-dimensional (M3D) integration of memristor arrays with silicon transistors facilitates energy-efficient parallel data processing and attains high-density arrays, representing a breakthrough approach for in-memory computing systems. In this study, we designed and fabricated a 1-kbit M3D integration of TiOx memristor (1 M) and the transmission gate-inverter circuit comprising of four MOSFETs as a transistor-selector (1TS), confirming both operational voltage range and current levels between 1 M and 1TS are well aligned. The designed 1TS efficiently eradicates voltage drops and substantially alleviates sneak current due to its high ON/ OFF ratio of 7.18 x 107, providing robust binary inputs with lower power consumption. Essential synaptic functions for 1-kbit 1 M and 1TS-1M arrays were validated, demonstrating consistent and robust LTP and LTD functions across 3000 pulses, with varying learning rates corresponding to the programming voltage schemes. Our 1-kbit 1TS-1M array architecture has the potential to be scaled to a 1.14 Tbit crossbar array without cell interference, becoming one of the largest M3D of memristor array configurations for in-memory computing and suggesting its capability to operate complex models. It demonstrates the viability of deploying a large-scale inmemory computing system efficient for accurately learning and recognizing complex tasks. This 1TS-1M array system achieved up to 79.47 % and 84.89 % recognition accuracies for the CIFAR-10 and UTK face images dataset, respectively, even in the limited convolution and pooling layers in the convolution neural network (CNN).

关键词： in-memory computing CMOS-integrated memristor array 1TS-1M Convolutional neural network Artificial neural networks Sneak current

来源：评论

学校读者我要写书评

暂无评论

Reconfigurable Logic and in-memory computing Based on Electrically Controlled Charge Trapping in Dielectric Engineered 2D Semiconductor Transistors

引用

ADVANCED FUNCTIONAL MATERIALS 2025年第13期35卷

作者： Tan, Dongxin Luo, Zheng-Dong Yang, Qiyu Xiao, Fei Gan, Xuetao Zhang, Dawei Chu, Zhufei Xue, Fei Zhang, Junpeng Xia, Yinshui Liu, Yan Hao, Yue Han, Genquan Xidian Univ Hangzhou Inst Technol Hangzhou 311200 Peoples R China Xidian Univ Sch Microelect State Key Discipline Lab Wide Band Gap Semicond Te Xian 710071 Peoples R China Northwestern Polytech Univ Minist Ind & Informat Technol Key Lab Light Field Manipulat & Informat Acquisit Xian 710129 Peoples R China Northwestern Polytech Univ Sch Phys Sci & Technol Shaanxi Key Lab Opt Informat Technol Xian 710129 Peoples R China UNSW Sydney Sch Mat Sci & Engn Sydney NSW 2052 Australia UNSW Sydney ARC Ctr Excellence Future Low Energy Elect Technol Sydney NSW 2052 Australia Ningbo Univ Fac Elect Engn & Comp Sci Ningbo 315211 Peoples R China Zhejiang Univ Ctr Quantum Matter Sch Phys Hangzhou 310027 Peoples R China Zhejiang Univ ZJU Hangzhou Global Sci & Technol Innovat Ctr Hangzhou 311215 Peoples R China Xidian Univ Sch Artificial Intelligence Xian 710071 Peoples R China

The co-integration of logic, memory, synapse, and other essential functionalities into one single element with run-time reconfigurability is explored as a promising approach for an efficient and flexible in-memory computing platform. However, despite ample research focused on such reconfigurable semiconductor technology, it remains challenging to achieve a CMOS-compatible device concept that is with simplified device structure, versatile functionalities, and efficient operation schemes. Here, a new type of run-time electrically reconfigurable device is demonstrated based on dielectric-engineered 2D semiconductor transistors. With an engineered semiconductor/charge-trap layer/dielectric film heterostructure, the 2D charge-trap transistor (CTT) resembles a simplified metal-oxide-semiconductor field-effect transistor (MOSFET) structure. Both multilevel permanent charge trapping and transient voltage-modulating capabilities can be realized in the 2D CTTs, giving rise to various switchable device function modes including non-volatile memory, threshold voltage-variable logic switch, and artificial synapse. Leveraging the monolithic integration of multiple 2D CTTs and time-sequential reconfigurable operation strategy, high-performance logic inverter and non-volatile ternary content-addressable memory (TCAM) with compact architecture can be created. The performance of the 2D CTTs in synapse mode is evaluated with the simulation of the convolutional neural network, showing great potential for future neuromorphic computing hardware.

关键词： 2D transistors charge trapping effect in-memory computing non-volatile memory reconfigurable devices

来源：评论

学校读者我要写书评

暂无评论

3-D Vertical Resistive Switching Random Access memory (3D-VRRAM) With Multilevel Programming for High-Density, Energy-Efficient in-memory computing

引用

IEEE TRANSACTIONS ON ELECTRON DEVICES 2025年

作者： Bridarolli, D. Zucchelli, C. Mannocci, P. Ricci, S. Farronato, M. Pedretti, G. Sun, Z. Ielmini, D. Politecn Milan Dipartimento Elettron Informaz & Bioingn DEIB I-20133 Milan Italy IU NET I-20133 Milan Italy Hewlett Packard Labs Artificial Intelligence Res Lab AIRL Milpitas CA 95035 USA Peking Univ Inst Artificial Intelligence Sch Integrated Circuits Beijing 100871 Peoples R China

Resistive random access memory (RRAM) devices offer a broad range of attractive properties for in-memory computing (IMC) applications, such as nonvolatile storage, low read current, and high scalability. IMC allows to overcome the memory bottleneck of data-intensive workloads, such as deep learning on the edge. In this context, 3-D vertical RRAM (3D-VRRAM) is a promising option to achieve high memory cell capacity with low fabrication cost. In this work, we present an HfOx-based 3D-VRRAM crossbar array (CBA) capable of IMC with precise multilevel programming. We show an extensive experimental demonstration of both matrix-vector multiplication (MVM) and inverse/pseudoinverse matrix calculation via IMC on 3D-VRRAM. To further support the parallel IMC application in real-life scenarios, the work also reports a demonstration of relatively large-size problems adopting 2D-RRAM and SRAM-based memory arrays. These results support 3D-VRRAM for high-density, energy-efficient IMC for edge computing applications.

关键词： Semiconductor device measurement Three-dimensional displays Energy efficiency Electrodes Silicon compounds Programming in-memory computing Hafnium compounds Current measurement Scanning electron microscopy Edge computing embedded memory in-memory computing (IMC) monolithic 3-D integration resistive random access memory (RRAM) scaling

来源：评论

学校读者我要写书评

暂无评论

In Situ Analog in-memory computing Under Ionizing Radiation Exposure

引用

IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第4期72卷 1243-1251页

作者： Xiao, T. Patrick Siath, Maximilian Spear, Matthew Wilson, Donald Bennett, Christopher H. Feinberg, Ben Hughart, David R. Neuendank, Jereme Brown, William E. Barnaby, Hugh Agrawal, Vineet Puchner, Helmut Agarwal, Sapan Marinella, Matthew J. Sandia Natl Labs Albuquerque NM 87185 USA Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA Ellutions LLC Chandler AZ 85286 USA Infineon Technol San Jose CA 95037 USA Sandia Natl Labs Livermore CA 94550 USA

We experimentally performed in situ analog in-memory computing (IMC) under ionizing radiation, using a 40-nm silicon-oxide-nitride-oxide-silicon (SONOS) charge-trap memory array with peripheral circuits that support analog matrix-vector multiplication (MVM) operations. The SONOS array used analog MVMs to process the last layer of a convolutional neural network (CNN) for TinyImageNet image classification while being irradiated by gamma rays from a Co-60 source. We experimentally characterized how the following quantities were gradually degraded by increasing the total ionizing dose (TID), up to 3.2 Mrad(Si): neural network weights that were mapped to SONOS states, dot products that were computed by analog MVMs, and the resulting image classification accuracy of the neural network. Using multiscale modeling, we confirmed that the experimentally observed accuracy loss originates almost entirely from the state-dependent current shifts induced by ionizing radiation in the SONOS memory cells. Our experimentally validated model of radiation effects in SONOS analog computing can be used to guide the design of reliable space-grade analog IMC accelerators.

关键词： SONOS devices Convolutional neural networks Accuracy Neural networks Vectors Ionizing radiation in-memory computing Training Threshold voltage Logic gates Analog computing charge-trap memory flash memory in-memory computing (IMC) ionizing radiation machine learning (ML) neural networks silicon-oxide-nitride-oxide-silicon (SONOS) total ionizing dose (TID)

来源：评论

学校读者我要写书评

暂无评论

A Violet-Light-Responsive ReRAM Based on Zn2SnO4/Ga2O3 Heterojunction as an Artificial Synapse for Visual Sensory and in-memory computing

引用

ADVANCED ELECTRONIC MATERIALS 2025年第3期11卷

作者： Shrivastava, Saransh Dai, Wei-Sin Limantoro, Stephen Ekaputra Juliano, Hans Tseng, Tseung-Yuen Natl Yang Ming Chiao Tung Univ Inst Elect Hsinchu 30010 Taiwan Natl Yang Ming Chiao Tung Univ Dept Elect Engn & Comp Sci Hsinchu 30010 Taiwan

Due to the imitation of the neural functionalities of the human brain via optical modulation of resistance states, photoelectric resistive random access memory (ReRAM) devices attract extensive attraction for synaptic electronics and in-memory computing applications. In this work, a photoelectric synaptic ReRAM (PSR) of the structure of ITO/Zn2SnO4/Ga2O3/ITO/glass with a simple fabrication process is reported to imitate brain plasticity. Electrically induced long-term potentiation/depression (LTP/D) behavior indicates the fulfillment of the fundamental requirement of artificial neuron devices. Classification of three-channeled images corrupted with different levels (0.15-0.9) of Gaussian noise is achieved by simulating a convolutional neural network (CNN). The violet light (405 nm) illumination generates excitatory post synaptic current (EPSC), which is influenced by the persistent photoconductivity (PPC) effect after discontinuing the optical excitation. As an artificial neuron device, PSR is able to imitate some basic neural functions such as multi-levels of photoelectric memory with linearly increasing trend, and learning-forgetting-relearning behavior. The same device also shows the emulation of visual persistency of optic nerve and skin-damage warning. This device executes high-pass filtering function and demonstrates its potential in the image-sharpening process. These findings provide an avenue to develop oxide semiconductor-based multifunctional synaptic devices for advanced in-memory photoelectric systems.

关键词： in-memory computing photoelectric ReRAM synaptic electronics violet light stimulation visual sensory wide bandgap oxide semiconductor

来源：评论

学校读者我要写书评

暂无评论

IMPACT: in-memory computing Architecture based on Y-FlAsh Technology for Coalesced Tsetlin machine inference

引用

PHILOSOPHICAL TRANSACTIONS OF THE ROYAL SOCIETY A-MATHEMATICAL PHYSICAL AND ENGINEERING SCIENCES 2025年第2288期383卷 20230393页

作者： Ghazal, Omar Wang, Wei Kvatinsky, Shahar Merchant, Farhad Yakovlev, Alex Shafik, Rishad Newcastle Univ Sch Engn Microsyst Grp Newcastle Upon Tyne NE1 7RU England Peng Cheng Lab Shenzhen Peoples R China Technion Israel Inst Technol Haifa Israel Bernoulli Inst Groningen Netherlands CogniGron Groningen Netherlands

The increasing demand for processing large volumes of data for machine learning (ML) models has pushed data bandwidth requirements beyond the capability of traditional von Neumann architecture. in-memory computing (IMC) has recently emerged as a promising solution to address this gap by enabling distributed data storage and processing at the micro-architectural level, significantly reducing both latency and energy. In this article, we present in-memory computing architecture based on Y-FlAsh technology for Coalesced Tsetlin machine inference (IMPACT), underpinned on a cutting-edge memory device, Y-Flash, fabricated on a 180 nm complementary metal oxide semiconductor (CMOS) process. Y-Flash devices have recently been demonstrated for digital and analogue memory applications;they offer high yield, non-volatility and low power consumption. IMPACT leverages the Y-Flash array to implement the inference of a novel ML algorithm: coalesced Tsetlin machine (CoTM) based on propositional logic. CoTM utilizes Tsetlin automata (TA) to create Boolean feature selections stochastically across parallel clauses. IMPACT is organized into two computational crossbars for storing the TA and weights. Through validation on the MNIST dataset, IMPACT achieved 96.3 % accuracy. IMPACT demonstrated improvements in energy efficiency, e.g. factors of 2.23 over CNN-based ReRAM, 2.46 over neuromorphic using NOR-Flash and 2.06 over DNN-based phase-change memory (PCM), suited for modern ML inference *** article is part of the theme issue 'Emerging technologies for future secure computing platforms'.

关键词： Coalesced Tsetlin machine in-memory computing non-volatile memristor AI inference architecture

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：