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TAICHI: A Tiled Architecture for in-memory computing and Heterogeneous Integration

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2022年第2期69卷 559-563页

作者： Wang, Xinxin Pinkham, Reid Zidan, Mohammed A. Meng, Fan-Hsuan Flynn, Michael P. Zhang, Zhengya Lu, Wei D. Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA

We present TAICHI, a general in-memory computing deep neural network accelerator design based on RRAM crossbar arrays heterogeneously integrated with local arithmetic units and global co-processors to allow the system to efficiently map different models while maintaining high energy efficiency and throughput. A hierarchical mesh network-on-chip is implemented to facilitate communication among clusters in TAICHI to balance reconfigurability and efficiency. Detailed deployment of the different circuit components is discussed, and the system performance is estimated at several technology nodes. The heterogeneous design also allows the system to accommodate models larger than the on-chip storage capability.

关键词： Computer architecture Gold Arrays Adders Bandwidth Kernel Computational modeling DNN accelerator in-memory computing heterogeneous architecture tiled architecture RRAM

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3D Ferrimagnetic Device for Multi-Bit Storage and Efficient in-memory computing

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON DEVICE LETTERS 2021年第2期42卷 152-155页

作者： Zhang, Zhizhong Zheng, Zhenyi Zhang, Yue Sun, Jinyi Lin, Kelian Zhang, Kun Feng, Xueqiang Chen, Lei Wang, Jinkai Wang, Guanda Du, Yinchang Zhang, Youguang Bournel, Arnaud Amiri, Pedram Khalili Zhao, Weisheng Beihang Univ Fert Beijing Inst Beijing Adv Innovat Ctr Big Data & Brain Computat Sch Microelect Beijing 100191 Peoples R China Beihang Univ Nanoelect Sci & Technol Ctr Hefei Innovat Res Inst Hefei 230013 Peoples R China Univ Paris Saclay Ctr Nanosci & Nanotechnol F-91120 Palaiseau France Northwestern Univ Dept Elect & Comp Engn Evanston IL 60208 USA

In this letter, we propose a 3D spintronic device stacked by ferrimagnetic (FIM) alloy CoTb layers with a thickness gradient for realizing multi-bit storage and efficient in-memory computing (IMC). Firstly, spin-orbit torque (SOT) induced multi-level magnetization switching of a Pt/CoTb/W/CoTb/Pt stack is experimentally achieved and micromagnetically modeled. Furthermore, a 3D-FIM IMC device with multiple ferrimagnetic layers is constructed and analyzed. Its functionalities of ultra-dense storage and reconfigurable logic are both validated through micromagnetic studies. Due to the ultra-fast dynamics near the compensation point, this 3D-FIM IMC device can operate with ultra-low energy consumption (similar to 18 aJ) and ultra-high speed (similar to 25 ps).

关键词： Ferrimagnet three-dimension multi-bit in-memory computing reconfigurable logic

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Custom RISC-V architecture incorporating memristive in-memory computing

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AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2024年 187卷

作者： Mallios, Konstantinos Alexandros Tompris, Ioannis Passias, Athanasios Ntinas, Vasileios Fyrigos, Iosif-Angelos Sirakoulis, Georgios Ch. Democritus Univ Thrace Dept Elect & Comp Engn Kimeria 67100 Xanthi Greece Tech Univ Dresden Inst Circuits & Syst Fac Elect & Comp Engn D-01069 Dresden Germany

Due to the rise in data-intensive applications, the von Neumann bottleneck is increasingly restricting modern computer architectures, resulting to latency and energy consumption. Addressing this challenge necessitates a CMOS-compatible solution with high energy efficiency and significant parallelism. Utilizing resistive switching components within a 1T1R crossbar array and the application of Stanford RRAM model, this paper suggests an original method for in-memory computing. Moreover, this work shows a new way to advance the popular RISC-V architecture by including memristive crossbar array. It does this by adding a custom instruction set, special hardware blocks, and the Scouting Logic Scheme. These modifications serve both as a comprehensive testbed for the memory system and a proof of concept for the future integration of memristors in computing architectures. The proposed design undergoes extensive testing and power analysis to validate its functionality and performance under various conditions. The results demonstrate significant improvements in computational efficiency and energy savings, highlighting the potential of memristor-based in-memory computing systems to overcome current architectural limitations.

关键词： in-memory computing RRAM crossbar RISC-V

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A Crossbar-Based in-memory computing Architecture

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2020年第12期67卷 4224-4232页

作者： Wang, Xinxin Zidan, Mohammed A. Lu, Wei D. Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA

To address the von Neumann bottleneck that leads to both energy and speed degradations, in-memory processing architectures have been proposed as a promising alternative for future computing applications. In this paper, we present an in-memory computing system based on resistive random-access memory (RRAM) crossbar arrays that is reconfigurable and can potentially perform parallel and general computing tasks. The system consists of small look-up tables (LUTs), a memory block, and two search auxiliary blocks, all implemented in the same RRAM crossbar array. External data access and data conversions are eliminated to allow operations fully in-memory. Details of addition, AND logic and multiplication operations are discussed on the basis of search and writeback steps. A compact instruction set consisting of 10 instructions is demonstrated on this architecture through circuit level simulations. Performance evaluations show that the proposed in-memory computing architecture is suitable for handling data-intensive problems. The average power consumption of the crossbar chip is estimated to be 45 mu W.

关键词： Table lookup Resistance Switches Arrays Performance evaluation MOS devices in-memory computing RRAM crossbar array look-up table (LUT)

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IMPLY-Based High-Speed Conditional Carry and Carry Select Adders for in-memory computing

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IEEE TRANSACTIONS ON NANOTECHNOLOGY 2023年 22卷 280-290页

作者： Kaushik, Nandit Bodapati, Srinivasu Indian Inst Technol Sch Comp & Elect Engn Mandi 175005 India

Big data applications involved with neural networks requires frequent data transfer between memory and processing elements and thus, take a significant portion of energy. One possible method is to realize logic operations inside the memory, often known as in-memory computing. The memristor employed in a crossbar can also conduct logic operations, making it a promising candidate for enabling such designs. in-memory computing can vastly improve speed efficiency by significantly reducing memory access time and energy. Therefore, efficient operations inside the memory are crucial for data-intensive applications. This article presents two high-speed adders in memristive technology, which are derived using IMPLY-based logic operations and can be implemented on a crossbar architecture for in-memory computing. One is a carry select adder, which uses efficient ripple carry adders and multiplexers. While the other is a conditional carry adder, designed using a modified half adder and multiplexers. An IMPLY-based multiplexer and modified half adder are proposed as part of these adders. A modified half adder calculates the sum of two inputs and two carry outputs for various carry inputs. Compared to conventional adder designs, the speed of these two adders has been significantly enhanced. In particular, the proposed 32-bit Carry Select Adder and Conditional Carry Adder take 123 and 90 computational steps, respectively. The proposed adders have improved the speed by 30% and 49%, respectively, compared to the best-existing adder in IMPLY. Further, this article presents computational steps and the number of memristors required for $n$-bit adders. The proposed circuits were simulated using the VTEAM model, and energy consumed for each adder is calculated from the simulations.

关键词： Adder carry select conditional carry memristor imply and emerging technologies in-memory computing

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Enabling Energy-Efficient in-memory computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array

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IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 2023年第1期13卷 445-455页

作者： Soundrapandiyan, Kavitha Vishvakarma, Santosh Kumar Reniwal, Bhupendra Singh IIITDM Kancheepuram Dept Elect & Commun Chennai 600127 India Indian Inst Technol Indore Dept Elect Engn Indore 453552 Madhya Pradesh India Indian Inst Technol IIT Jodhpur Dept Elect Engn Jodhpur 342030 Rajasthan India

With the increasing gap between processing speed and memory bandwidth necessity for in/near-memory computing has emerged, to ensure high-performance, energy-efficient computing for data-intensive applications at the edge. This work proposes a feasible SRAM compute cache with a sense amplifier (SA) based approach to perform in-/near memory Boolean computations with a novel reconfigurable assist sense amplifier (RASA). The RASA exploits assist transistors to achieve NAND, NOR and XNOR operations without affecting the transparency of normal read leading to fast and reliable sensing with only one SA. This effectively eliminates the need for two SAs in comparison to state-of-the-art solutions. The proposed work improves memory density and reduces cost-per-bit by leveraging the SA-based approach because existing solutions lead to significant area overhead/cell which reflects overhead multiply by the number of cells/column. The RASA provides flexibility to accommodate more cells per column at the architecture level. Extensive Monte-Carlo analysis is performed to verify the feasibility of the proposed circuit in commercial 65nm UMC technology under iso-SA area and iso-yield conditions. Simulations indicate a 34.34%, 84.87%, 81.21%, 75.46% improvement in energy, and a 71.30%, 43.36%, 32.49%, 17.44% improvement in throughput leading to a reduction of 60.97%, 91.37%, 87.22%, 79.62% in energy-delay product with respect to CLSA (Dong et al., 2018), CSRAM (Chen et al., 2021), RRCSA (Rajput et al., 2022) and the ADSA (Agrawal et al., 2018) respectively. An improvement in the area of SA by 36.512% is achieved with respect to RRCSA.

关键词： Random access memory Computer architecture in-memory computing Decoding Bandwidth Arithmetic Transistors Assist device sense amplifier in memory computing digital Boolean logic

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Brain-Inspired Recognition System Based on Multimodal in-memory computing Framework for Edge AI

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第5期71卷 2294-2307页

作者： Xiao, He Xie, Dirui Hu, Xiaofang Zhou, Yue Zhou, Guangdong Duan, Shukai Southwest Univ Coll Artificial Intelligence Chongqing 400715 Peoples R China Chongqing Key Lab Brain Inspired Comp & Intelligen Chongqing 400715 Peoples R China

With the rapid development of edge devices, the deployment of AI on these devices has become a focal point for researchers. Moreover, the emergence of multimodal neural networks has facilitated the development and application of brain-inspired cognitive and recognition systems. However, the limited storage and computing resources of edge devices, along with the robustness issues of computational circuits, pose significant challenges in implementing AI systems with brain-inspired recognition capabilities on edge devices. To address this, we propose a memristor-based brain-inspired recognition (MBR) system, which can mimic the brain's information processing mechanism without additional cross-modal processing, making its behavior more akin to human responses. In addition, the proposed MBR system is implemented using the multimodal in-memory computing (IMC) framework and validated the robustness and effectiveness of the proposed system through simulation analyzing. Furthermore, the multimodal sentiment analysis (MSA) and emotion recognition in conversation (ERC) tasks are implemented on the MBR system with only one single training process. The results demonstrate the proposed system achieves superior performance compared to most existing baseline methods. Lastly, since the MBR system relies on memristor-based matrix multiplication, it emerges as one of the promising solutions for edge-based brain-inspired recognition applications.

关键词： Memristor brain-inspired circuits and systems in-memory computing multimodal edge AI

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An Efficient in-memory computing Architecture for Image Enhancement in AI Applications

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IEEE ACCESS 2022年 10卷 48229-48241页

作者： Bettayeb, Meriem Zayer, Fakhreddine Abunahla, Heba Gianini, Gabriele Mohammad, Baker Khalifa Univ Sci & Technol Elect Engn & Comp Sci Dept Syst Chip Lab Abu Dhabi U Arab Emirates Khalifa Univ Sci & Technol Ctr Autonomous Robot Syst KUCARS Abu Dhabi U Arab Emirates Univ Milan Dept Comp Sci I-20133 Milan Italy Khalifa Univ Sci & Technol Emirates Innovat Ctr EBTIC Abu Dhabi U Arab Emirates

Random spray retinex (RSR) is an effective image enhancement algorithm owing to its effectiveness in improving the image quality. However, the computing complexity of the algorithm, the required hardware resources, and memory access hamper its deployment in many application scenarios, for instance, in IoT systems with limited hardware resources. With the rise of artificial intelligence (AI), the use of image enhancement has become essential for improving the performance of many emerging applications. In this paper, we propose the use of RSR as a preprocessing filter before the task of semantic segmentation of low-quality urban road scenes. Using the publicly available Cityscapes dataset, we compared the performance of a pre-trained deep semantic segmentation network on dark and noisy images with that of RSR preprocessed images. Our findings confirm the effectiveness of RSR in improving segmentation accuracy. In addition, to address the computational complexity and suitability of edge devices, we propose a novel and efficient implementation of RSR using resistive random access memory (RRAM) technology. This architecture provides highly parallel analog in-memory computing (IMC) capabilities. A detailed, efficient, and low-latency implementation of RSR using RRAM-CMOS technology is described. The design was verified using SPICE simulations with measured data from the fabricated RRAM and 65 nm CMOS technologies. The approach presented here represents an important step towards a low-complexity, real-time hardware-friendly architecture and the design of retinex algorithms for edge devices.

关键词： Computer architecture Image color analysis Field programmable gate arrays Memristors Image segmentation Visualization Image enhancement Memristor crossbar multiply and add (MAC) operations random spray retinex scale-to-max filtering in-memory computing

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Impact of Aging and Process Variability on SRAM-Based in-memory computing Architectures

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第6期71卷 2696-2708页

作者： Shaik, Jani Babu Guo, Xinfei Singhal, Sonal Cyient Ltd SEMICON BU Hyderabad 500081 India Shanghai Jiao Tong Univ Univ Michigan Shanghai Jiao Tong Univ Joint Inst Shanghai 200240 Peoples R China Shiv Nadar Univ Dept Elect Engn Greater Noida 201314 India

As the SRAM-based in-memory computing (IMC) paradigm arises as a promising candidate to break the memory wall bottleneck and deliver optimal energy efficiency, reliability has been paid less attention. Serious reliability issues that concern a conventional SRAM cell includes increased process variations as well as the dominant transistor aging mechanisms, such as Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) phenomena. These degradation impacts the speed, noise margin and input offset voltage a SRAM structure. Though the vulnerability of a SRAM cell to transistor aging has been extensively studied in the literature, there is still missing information on how aging impacts the SRAM-based IMC architectures along with the process variability. In this work, through simulation, we present a comprehensive study on impact of aging and process variability on commonly employed SRAM-based 6T-and 8T-IMC architectures. In the current study, degradation's stochastic behavior is examined by coupling process fluctuations brought on by aging. The confluences of two degradation mechanisms help to identify the worst-case failures. This study serves as one of the first ones that provide BTI induced aging analysis on multiple IMC logic operations and offer perspectives for designing robust SRAM-based IMC based architectures.

关键词： in-memory computing circuit reliability SRAM BTI HCI process variability

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Efficient and lightweight in-memory computing architecture for hardware security

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JOURNAL OF PARALLEL AND DISTRIBUTED computing 2024年 190卷

作者： Ajmi, Hala Zayer, Fakhreddine Fredj, Amira Hadj Belgacem, Hamdi Mohammad, Baker Werghi, Naoufel Dias, Jorge Univ Monastir Fac Sci Monastir FSM Elect & Microelect Monastir Tunisia Khalifa Univ Ctr Autonomous Robot Syst KUCARS Elect & Elect Engn Abu Dhabi U Arab Emirates Fac Sci Monastir Lab Elect & Microelect Monastir Tunisia High Inst Appl Sci & Technol Sousse Sousse Tunisia Fac Sci Monastir FSM Lab Elect & Microelect Monastir Tunisia Khalifa Univ EECS Abu Dhabi U Arab Emirates Qualcomm Austin TX USA Univ Edinburgh Div Informat Edinburgh Scotland Univ Glasgow Dept Comp Sci Glasgow Scotland Khalifa Univ Elect Engn & Comp Sci Dept Abu Dhabi U Arab Emirates Khalifa Univ Elect Engn & Comp Sci Dept Abu Dhabi U Arab Emirates Univ Louisville Louisville KY USA Univ Florence Florence Italy Univ Lille Lille France Children Natl Hlth Syst Washington Washington DC USA Korean Adv & Inst Sci & Technol Daejeon South Korea Univ Canberra Canberra ACT Australia Khalifa Univ Abu Dhabi U Arab Emirates

This paper introduces an innovative solution for improving the efficiency and speed of the Advanced Encryption Standard (AES) based cryptographic algorithm. The approach leverages in -memory computing (IMC) and is versatile for application across a broad spectrum of IoT applications, including robotic autonomous vehicles and various other scenarios. To achieve this goal, memristor (MR) designs are proposed to emulate the arithmetic operations required for different phases of the AES algorithm, enabling efficient in -memory processing. The key contributions of this work include;1) The development of a 4 bit -MR state element for implementing different arithmetic operations in an AES hardware prototype;2) The creation of a pipeline AES design for massive parallelism and MR integration compatibility;and 3) The hardware implementation of the AES-IMC based architecture using the MR emulator. The results show that AES-IMC performs better than existing architectures in terms of higher throughput and energy efficiency. Compared to conventional AES hardware, AES-IMC achieves a 30% power enhancement with comparable throughput. Additionally, when compared to state-of-the-art AESbased NVM engines, AES-IMC demonstrates comparable power dissipation and a 62% increase in throughput. The IMC architecture enables cost-effective real-time deployment of AES, leading to high-performance computing. By leveraging the power of in -memory computing, this system is able to provide improved computational efficiency and faster processing speeds, making it a promising solution for a wide range of applications in the field of autonomous driving and robotics. The potential benefits of this system include improved safety and security of unmanned devices, as well as enhanced performance and cost-effectiveness in a variety of computing environments.

关键词： AES Algorithm Hardware Security Memristor Technology in-memory computing Memristor Hardware

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