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Reconfigurable Stateful Logic Circuit With Cu/CuI/Pt Memristors for in-memory computing

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2024年第5期32卷 835-847页

作者： Luo, Li Li, Bochang Wang, Lidan Tan, Jinpei Duan, Shukai Zhu, Chunxiang Southwest Univ Coll Artificial Intelligence Chongqing 400715 Peoples R China Natl Univ Singapore Dept Elect & Comp Engn Singapore 117583 Singapore Natl Univ Singapore Dept Elect & Comp Engn Singapore 117583 Singapore Xidian Univ Hangzhou Inst Technol Emerging Device & Chip Lab Hangzhou 311200 Peoples R China

A memristive stateful logic circuit can provide a non-von Neumann computing architecture for integrating computation and storage. However, the stateful logic circuit based on memristors presents challenges in terms of computational complexity, reconfigurability, crossbar array compatibility, and sneak path problems. In this article, we propose a fully memristive circuit structure, which realizes all 16 Boolean logic operations with the same circuit topology. Because of the use of the same logic variable for input and output, no additional circuitry is required for logic cascading, which is beneficial to enable complicated computing tasks. The proposed stateful logic operations are experimentally demonstrated within Cu/CuI/Pt memristor crossbar array. The application of the presented logic design is further extended to a one-transistor-one-memristor (1T1M) crossbar array, overcoming the sneak path problem. Moreover, stateful logic operations can be performed in columns, rather than solely in rows, improving the computing capability and flexibility of the 1T1M array. The feasibility and reliability of this logic design in a 1T1M array are verified using two case studies of the adder-subtractor combination and the multiplexer. Our presented logic design shows superior performance in logic completeness, computational complexity, reconfigurability, logic cascading, parallel computing, and sneak path, which opens up an avenue for next-generation in-memory computing.

关键词： Memristors Logic arrays Resistance Logic gates Logic design Computer architecture in-memory computing Crossbar array in-memory computing memristor reconfigurability stateful logic

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IMCS2: Novel Device-to-Architecture Co-Design for Low-Power in-memory computing Platform Using Coterminous Spin Switch

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IEEE TRANSACTIONS ON MAGNETICS 2018年第7期54卷 1-14页

作者： Parveen, Farhana Angizi, Shaahin He, Zhezhi Fan, Deliang Univ Cent Florida Dept Elect & Comp Engn Orlando FL 32816 USA

Spin switch (SS) is a promising spintronic device which exhibits compactness, low power, non-volatility, input-output isolation leveraging giant spin Hall effect, spin transfer torque, and dipolar coupling. In this paper, we propose a novel device-to-architecture co-design for an in-memory computing platform using coterminous SS (IMCS2), which could simultaneously work as non-volatile memory and reconfigurable in-memory logic (AND/NAND, OR/NOR, and XOR/XNOR) without add-on logic circuits to memory chip. The computed logic output could be simply read out like a normal magnetic random access memory bit cell using the shared memory peripheral circuits. Such intrinsic in-memory logic could be used to process data within memory to greatly reduce power-hungry and long distance data communication in the conventional von Neumann computing system. The IMCS2-based in-memory bulk bitwise Boolean vector operation shows similar to 9x energy saving and similar to 3x speedup compared with that of DRAM-based in-memory computing platform. We further employ in-memory multiplication to evaluate the performance of the proposed in-memory computing platform for vector-vector multiplication with different vector sizes.

关键词： Giant spin Hall effect (GSHE) in-memory computing memory architecture reconfigurable logic spin switch (SS)

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HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM in-memory computing Accelerator for Dynamic Sparse Self-Attention in Transformer

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2024年第2期32卷 269-282页

作者： Liu, Shiwei Mu, Chen Jiang, Hao Wang, Yunzhengmao Zhang, Jinshan Lin, Feng Zhou, Keji Liu, Qi Chen, Chixiao Fudan Univ State Key Lab Integrated Chips & Syst Shanghai 200433 Peoples R China Zhangjiang Lab Shanghai 201210 Peoples R China

Self-attention-based transformers have outperformed recurrent and convolutional neural networks (RNN/ CNNs) in many applications. Despite the effectiveness, calculating self-attention is prohibitively costly due to quadratic computation and memory requirements. To solve this challenge, this article proposes a hybrid analog-ReRAM and digital-SRAM in-memory computing accelerator (HARDSEA), a computing-in-memory (CIM) accelerator supporting self-attention in transformer applications. To trade off between energy efficiency and algorithm accuracy, HARDSEA features an algorithm-architecture-circuit codesign. A product-quantization-based scheme dynamically facilitates self-attention sparsity by predicting lightweight token relevance. A hybrid in-memory computing architecture employs both high-efficiency analog ReRAM-CIM and high-precision digital SRAM-CIM to implement the proposed new scheme. The ReRAM-CIM, whose precision is sensitive to circuit nonidealities, takes charge of token relevance prediction where only computing monotonicity is demanded. The SRAM-CIM, utilized for exact sparse attention computing, is reorganized as an on-memory-boundary computing scheme, thus adapting to irregular sparsity patterns. In addition, we propose a time-domain winner-take-all (WTA) circuit to replace the expensive ADCs in ReRAM-CIM macros. Experimental results show that HARDSEA prunes BERT and GPT-2 models to 12%-33% sparsity without accuracy loss, achieving 13.5x13.5x- 28.5x28.5x speedup and 291.6x291.6x- 1894.3x1894.3x energy efficiency over GPU. Compared to state-of-the-art transformer accelerators, HARDSEA has 1.2x1.2x- 14.9x14.9x better energy efficiency at the same level of throughput.

关键词： Algorithm-architecture-circuit co-design in-memory computing self-attention transformer

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A Hybrid SRAM/RRAM in-memory computing Architecture Based on a Reconfigurable SRAM Sense Amplifier

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IEEE ACCESS 2023年 11卷 72159-72171页

作者： Nemati, Seyed Hassan Hadi Eslami, Nima Moaiyeri, Mohammad Hossein Shahid Beheshti Univ Fac Elect Engn Tehran *** Iran

In this paper, a hybrid memory architecture based on a new array of SRAM and resistive random-access memory (RRAM) cells is proposed to perform in-memory computing by implementing all basic two-input Boolean functions. The SRAM array can be configured as a dual-purpose element. It can be used as an SRAM array in memory mode to keep data for high-performance application requirements. It can also be configured as a sense amplifier (SA-SRAM) for reading the contents of RRAMs and performing the in-memory computation. The circuits are designed using independent-gate FinFET (IG-FinFET), whose channel is controlled by two independent gates, increasing the design's maneuverability. Our results indicate that the proposed SA-SRAM cells' write energy consumption and combined word line margin (CWLM) achieve 50% and 20% improvements compared to the conventional 8T SRAM. Moreover, by benefiting from the combination of SRAM and RRAM cells in the proposed architecture, the energy consumption of our design in application areas, such as image processing, is much lower than the well-known compared in-memory architecture designs. In addition, to address security concerns, we proposed a polymorphic circuit primitive to prevent reverse engineering or integrated circuit (IC) counterfeiting. The proposed polymorphic circuit also adds more computations to accomplish complex logic operations and the proposed hybrid memory architecture.

关键词： SRAM cell in-memory computing RRAM polymorphic IG-FinFET

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Bi-Directional and Operand-Controllable in-memory computing for Boolean Logic and Search Operations with Row and Column Directional SRAM (RC-SRAM)

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MICROMACHINES 2024年第8期15卷 1056-1056页

作者： Xiao, Han Zhao, Ruiyong Liu, Yulan Liu, Yuanzhen Chen, Jing Chinese Acad Sci Shanghai Inst Microsyst & Informat Technol Shanghai 200031 Peoples R China Univ Chinese Acad Sci Beijing 100049 Peoples R China

The von Neumann architecture is no longer sufficient for handling large-scale data. in-memory computing has emerged as the potent method for breaking through the memory bottleneck. A new 10T SRAM bitcell with row and column control lines called RC-SRAM is proposed in this article. The architecture based on RC-SRAM can achieve bi-directional and operand-controllable logic-in-memory and search operations through different signal configurations, which can comprehensively respond to various occasions and needs. Moreover, we propose threshold-controlled logic gates for sensing, which effectively reduces the circuit area and improves accuracy. We validate the RC-SRAM with a 28 nm CMOS technology, and the results show that the circuits are not only full featured and flexible for customization but also have a significant increase in the working frequency. At VDD = 0.9 V and T = 25 degrees C, the bi-directional search frequency is up to 775 MHz and 567 MHz, and the speeds for row and column Boolean logic reach 759 MHz and 683 MHz.

关键词： in-memory computing SRAM content-addressable memory Boolean logic operation

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Efficient Discrete Temporal Coding Spike-Driven in-memory computing Macro for Deep Neural Network Based on Nonvolatile memory

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第11期69卷 4487-4498页

作者： Han, Lixia Huang, Peng Wang, Yijiao Zhou, Zheng Zhang, Yizhou Liu, Xiaoyan Kang, Jinfeng Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China Beihang Univ Fert Beijing Inst Sch Integrated Circuit Sci & Engn MIIT Key Lab Spintron Beijing 100191 Peoples R China

Nonvolatile memory (NVM) based neural network can directly perform in situ computation in memory to significantly reduce energy consumption resulting from the data movement. However, the energy consumption by the analog-to-digital converter (ADC) restricts the efficiency of the mixed-signal in-memory computing macro. The rate coding spike-driven in-memory computing macro can increase the energy efficiency via eliminating the ADC, but the improvement is limited because substantial energy is consumed for the coding of multiple spikes. In this work, we propose a discrete temporal coding spike-driven in-memory computing macro, including input coding scheme, weight mapping method, and improved leaky integrate-and-fire (LIF) neuron circuit, to perform the efficient forward inference of deep neural networks based on NVM array. We then optimize the designment of the proposed in-memory computing macro to mitigate the neural network accuracy loss due to the nonlinearity of the LIF neuron and voltage drop caused by interconnect resistance. Because the temporal coding scheme reduces spike numbers and the improved-LIF circuit simultaneously integrates two bit-lines current corresponding to positive and negative weight, the proposed macro achieves 46.63TOPS/W energy efficiency and 1.92TOPS throughput for 3bit temporal coding precision.

关键词： Encoding in-memory computing Capacitors Biological neural networks Neurons Delays Nonvolatile memory in-memory computing deep neural network non-volatile memory discrete temporal coding spike-driven macro

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3D Ferrimagnetic Device for Multi-Bit Storage and Efficient in-memory computing

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON DEVICE LETTERS 2021年第2期42卷 152-155页

作者： Zhang, Zhizhong Zheng, Zhenyi Zhang, Yue Sun, Jinyi Lin, Kelian Zhang, Kun Feng, Xueqiang Chen, Lei Wang, Jinkai Wang, Guanda Du, Yinchang Zhang, Youguang Bournel, Arnaud Amiri, Pedram Khalili Zhao, Weisheng Beihang Univ Fert Beijing Inst Beijing Adv Innovat Ctr Big Data & Brain Computat Sch Microelect Beijing 100191 Peoples R China Beihang Univ Nanoelect Sci & Technol Ctr Hefei Innovat Res Inst Hefei 230013 Peoples R China Univ Paris Saclay Ctr Nanosci & Nanotechnol F-91120 Palaiseau France Northwestern Univ Dept Elect & Comp Engn Evanston IL 60208 USA

In this letter, we propose a 3D spintronic device stacked by ferrimagnetic (FIM) alloy CoTb layers with a thickness gradient for realizing multi-bit storage and efficient in-memory computing (IMC). Firstly, spin-orbit torque (SOT) induced multi-level magnetization switching of a Pt/CoTb/W/CoTb/Pt stack is experimentally achieved and micromagnetically modeled. Furthermore, a 3D-FIM IMC device with multiple ferrimagnetic layers is constructed and analyzed. Its functionalities of ultra-dense storage and reconfigurable logic are both validated through micromagnetic studies. Due to the ultra-fast dynamics near the compensation point, this 3D-FIM IMC device can operate with ultra-low energy consumption (similar to 18 aJ) and ultra-high speed (similar to 25 ps).

关键词： Ferrimagnet three-dimension multi-bit in-memory computing reconfigurable logic

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An Efficient in-memory computing Architecture for Image Enhancement in AI Applications

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IEEE ACCESS 2022年 10卷 48229-48241页

作者： Bettayeb, Meriem Zayer, Fakhreddine Abunahla, Heba Gianini, Gabriele Mohammad, Baker Khalifa Univ Sci & Technol Elect Engn & Comp Sci Dept Syst Chip Lab Abu Dhabi U Arab Emirates Khalifa Univ Sci & Technol Ctr Autonomous Robot Syst KUCARS Abu Dhabi U Arab Emirates Univ Milan Dept Comp Sci I-20133 Milan Italy Khalifa Univ Sci & Technol Emirates Innovat Ctr EBTIC Abu Dhabi U Arab Emirates

Random spray retinex (RSR) is an effective image enhancement algorithm owing to its effectiveness in improving the image quality. However, the computing complexity of the algorithm, the required hardware resources, and memory access hamper its deployment in many application scenarios, for instance, in IoT systems with limited hardware resources. With the rise of artificial intelligence (AI), the use of image enhancement has become essential for improving the performance of many emerging applications. In this paper, we propose the use of RSR as a preprocessing filter before the task of semantic segmentation of low-quality urban road scenes. Using the publicly available Cityscapes dataset, we compared the performance of a pre-trained deep semantic segmentation network on dark and noisy images with that of RSR preprocessed images. Our findings confirm the effectiveness of RSR in improving segmentation accuracy. In addition, to address the computational complexity and suitability of edge devices, we propose a novel and efficient implementation of RSR using resistive random access memory (RRAM) technology. This architecture provides highly parallel analog in-memory computing (IMC) capabilities. A detailed, efficient, and low-latency implementation of RSR using RRAM-CMOS technology is described. The design was verified using SPICE simulations with measured data from the fabricated RRAM and 65 nm CMOS technologies. The approach presented here represents an important step towards a low-complexity, real-time hardware-friendly architecture and the design of retinex algorithms for edge devices.

关键词： Computer architecture Image color analysis Field programmable gate arrays Memristors Image segmentation Visualization Image enhancement Memristor crossbar multiply and add (MAC) operations random spray retinex scale-to-max filtering in-memory computing

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Impact of Aging and Process Variability on SRAM-Based in-memory computing Architectures

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第6期71卷 2696-2708页

作者： Shaik, Jani Babu Guo, Xinfei Singhal, Sonal Cyient Ltd SEMICON BU Hyderabad 500081 India Shanghai Jiao Tong Univ Univ Michigan Shanghai Jiao Tong Univ Joint Inst Shanghai 200240 Peoples R China Shiv Nadar Univ Dept Elect Engn Greater Noida 201314 India

As the SRAM-based in-memory computing (IMC) paradigm arises as a promising candidate to break the memory wall bottleneck and deliver optimal energy efficiency, reliability has been paid less attention. Serious reliability issues that concern a conventional SRAM cell includes increased process variations as well as the dominant transistor aging mechanisms, such as Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) phenomena. These degradation impacts the speed, noise margin and input offset voltage a SRAM structure. Though the vulnerability of a SRAM cell to transistor aging has been extensively studied in the literature, there is still missing information on how aging impacts the SRAM-based IMC architectures along with the process variability. In this work, through simulation, we present a comprehensive study on impact of aging and process variability on commonly employed SRAM-based 6T-and 8T-IMC architectures. In the current study, degradation's stochastic behavior is examined by coupling process fluctuations brought on by aging. The confluences of two degradation mechanisms help to identify the worst-case failures. This study serves as one of the first ones that provide BTI induced aging analysis on multiple IMC logic operations and offer perspectives for designing robust SRAM-based IMC based architectures.

关键词： in-memory computing circuit reliability SRAM BTI HCI process variability

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A Heterogeneous in-memory computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks

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IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 2022年第2期12卷 422-435页

作者： Garofalo, Angelo Ottavi, Gianmarco Conti, Francesco Karunaratne, Geethan Boybat, Irem Benini, Luca Rossi, Davide Univ Bologna Dept Elect Elect & Informat Engn DEI I-40126 Bologna Italy IBM Res Europe CH-8803 Zurich Switzerland Swiss Fed Inst Technol IIS Integrated Syst Lab CH-8092 Zurich Switzerland

Deployment of modern TinyML tasks on small battery-constrained IoT devices requires high computational energy efficiency. Analog in-memory computing (IMC) using non-volatile memory (NVM) promises major efficiency improvements in deep neural network (DNN) inference and serves as on-chip memory storage for DNN weights. However, IMC's functional flexibility limitations and their impact on performance, energy, and area efficiency are not yet fully understood at the system level. To target practical end-to-end loT applications, IMC arrays must be enclosed in heterogeneous programmable systems, introducing new system-level challenges which we aim at addressing in this work. We present a heterogeneous tightly-coupled clustered architecture integrating 8 RISC-V cores, an in-memory computing accelerator (IMA), and digital accelerators. We benchmark the system on a highly heterogeneous workload such as the Bottleneck layer from a MobileNetV2, showing 11.5x performance and 9.5x energy efficiency improvements, compared to highly optimized parallel execution on the cores. Furthermore, we explore the requirements for end-to-end inference of a full mobile-grade DNN (MobileNetV2) in terms of IMC array resources, by scaling up our heterogeneous architecture to a multi-array accelerator. Our results show that our solution, on the end-to-end inference of the MobileNetV2, is one order of magnitude better in terms of execution latency than existing programmable architectures and two orders of magnitude better than state-of-the-art heterogeneous solutions integrating in-memory computing analog cores.

关键词： in-memory computing RISC-V heterogeneous computing architecture MobileNetV2

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