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7th International Conference of the Experience of Designing and Application of CAD Systems in Microelectronics

作者： Melnyk, A Salo, A Lviv Polytech Natl Univ Dept Comp Engn UA-79046 Lvov Ukraine

ISBN: (纸本)9665532782

There are lot of applications that demand intensive data streams processing in real time nowadays. These tasks are usually performed by dedicated or algorithm-specific computer systems. Such systems design is quite complicated and laborious process while time-to-market is critical. So there is a need for the computer-aided dedicated systems design methods development. In given work instruction set architecture of the determined memory access processor is proposed. Such a processor usage will grant very short terms of application-specific systems design.

关键词： computer architecture dedicated system determined memory access instruction set architecture

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The impact of x86 instruction set architecture on superscalar processing

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JOURNAL OF SYSTEMS architecture 2005年第1期51卷 63-77页

作者： Rico, R Pérez, JI Frutos, JA Univ Alcala de Henares Dept Comp Engn Alcala De Henares 28871 Spain

Performance improvement of x86 processors is a relevant matter. From the point of view of superscalar processing, it is necessary to complement the studies on instruction use with analogous ones on data use and, furthermore, analyze the data flow graphs, as its dependencies are responsible for limitations on ILP. In this work, using instruction traces from common applications, quantitative analyses of implicit operands, memory addressing and condition codes have been performed, three sources of significant limitations on the maximum achievable parallelism in the x86 architecture. In order to get a deeper knowledge of these limitations, the data dependence graphs are built from traces. By means of graph matrix representation, potentially exploitable parallelism is quantified and parallelism distributions from the traces are shown. The method has also been applied to measure the impact of the use of condition codes. Results are compared with previous work and some conclusions are presented relating the obtained degree of parallelism with negative characteristics of x86 instruction set architecture. (C) 2004 Elsevier B.V. All rights reserved.

关键词： instruction level parallelism instruction set architecture DDG-based quantification

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A Scheme to Improve the Intrinsic Error Detection of the instruction set architecture

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER architecture LETTERS 2017年第2期16卷 103-106页

作者： Martinez, Jorge A. Antonio Maestro, Juan Reviriego, Pedro Univ Antonio Nebrija C Pirineos 55 Madrid 28040 Spain

The instruction set architecture (ISA) determines the effect that a soft error on an instruction can have on the processor. Previous works have shown that the ISA has some intrinsic capability of detecting errors. For example, errors that change a valid instruction into an invalid instruction encoding or into an instruction that causes an exception. The percentage of detectable errors varies widely for each bit in the ISA. For example, errors on bits that are used for immediate or register values are unlikely to be detected while those that are used for the opcode are more likely to lead to an exception. In this paper, this is exploited by introducing a simple encoding of the instructions that does not require additional bits. The idea is that the decoding propagates the error so that it affects the most sensitive bit of the ISA and therefore it is more likely to be detected. As no additional bits are required, no changes or overheads are needed in the memory. The proposed scheme is useful when the memory is not protected with parity or Error Correction Codes. The only cost of implementing the technique are simple encoder and decoder circuits that are similar to a parity computation. This technique is applicable to any ISA, no matter the length of the opcodes or their location in the instruction encoding. The effectiveness of the proposed scheme has been evaluated on the ARM Cortex M0 ISA resulting in an increase in the error detection capability of up to 1.64x.

关键词： Soft error error detection instruction set architecture

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An Isabelle/HOL Formalisation of the SPARC instruction set architecture and the TSO Memory Model

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JOURNAL OF AUTOMATED REASONING 2021年第4期65卷 569-598页

作者： Hou, Zhe Sanan, David Tiu, Alwen Liu, Yang Hoa, Koh Chuen Dong, Jin Song Griffith Univ Sch Informat & Commun Technol Brisbane Qld Australia Nanyang Technol Univ Sch Comp Sci & Engn Singapore Singapore Australian Natl Univ Coll Engn & Comp Sci Canberra ACT Australia Singapore Def Sci Org Singapore Singapore Natl Univ Singapore Sch Comp Singapore Singapore

The SPARC instruction set architecture (ISA) has been used in various processors in workstations, embedded systems, and in mission-critical industries such as aviation and space engineering. Hence, it is important to provide formal frameworks that facilitate the verification of hardware and software that run on or interface with these processors. In this work, we give the first formal model formulti-coreSPARC ISA and Total Store Ordering (TSO) memory model in Isabelle/HOL. We present two levels of modelling for the ISA: The low-level ISA model, which isexecutable, covers many features specific to SPARC processors, such as delayed-write for control registers, windowed general registers, and more complex memory access. We have tested our model extensively against a LEON3 simulation board, the test covers both single-step executions and sequential execution of programs. We also prove some important properties for our formal model, including a non-interference property for the LEON3 processor. The high-level ISA model is an abstraction of the low-level model and it provides an interface for memory operations in multi-core processors. On top of the high-level ISA model, we formalise two TSO memory models: one is an adaptation of the axiomatic SPARC TSO model (Sindhu et al. in Formal specification of memory models, Springer, Boston, 1992;SPARC in The SPARC architecture manual version 8, 1992.), the other is a new operational TSO model which is suitable for verifying execution results. We prove that the operational model is sound and complete with respect to the axiomatic model. Finally, we give verification examples with two case studies drawn from the SPARCv9 manual.

关键词： instruction set architecture Form verification Isabelle/HOL Weak memory model TSO

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PISA-DMA: Processing-in-Memory instruction set architecture Using DMA

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IEEE ACCESS 2023年 11卷 8622-8632页

作者： Lee, Won Jun Kim, Chang Hyun Paik, Yoonah Kim, Seon Wook Korea Univ Dept Elect Engn Seoul 02841 South Korea

Processing-in-memory (PIM) has attracted attention to overcome the memory bandwidth limitation, especially for computing memory-intensive DNN applications. Most PIM approaches use the CPU's memory requests to deliver instructions and operands to the PIM engines, making a core busy and incurring unnecessary data transfer, thus, resulting in significant offloading overhead. DMA can resolve the issue by transferring a high volume of successive data without intervening CPU and polluting the memory hierarchy, thus perfectly fitting the PIM concept. However, the small computing resources of DRAM-based PIM devices allow us to transfer only small amounts of data at one DMA transaction and require a large number of descriptors, thus still incurring significant offloading overhead. This paper introduces PIM instruction set architecture (ISA) using a DMA descriptor called PISA-DMA to express a PIM opcode and operand in a single descriptor. Our ISA makes PIM programming intuitive by thinking of committing one PIM instruction as completing one DMA transaction and representing a sequence of PIM instructions using the DMA descriptor list. Also, PISA-DMA minimizes the offloading overhead while guaranteeing compatibility with commercial platforms. Our PISA-DMA eliminates the opcode offloading overhead and achieves 1.25x, 1.31x, and 1.29x speedup over the baseline PIM at the sequence length of 128 with the BERT, RoBERTa, and GPT-2 models, respectively, in ONNX runtime with real machines. Also, we study how our proposed PISA affects performance in compiler optimization and show that the operator fusion of matrix-matrix multiplication and element-wise addition achieved 1.04x speedup, a similar performance gain using conventional ISAs.

关键词： Engines Computer architecture Registers Switches DRAM chips Random access memory Programming Processing-in-DRAM direct memory access instruction set architecture PIM offloading

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RISC-V instruction set architecture Extensions: A Survey

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IEEE ACCESS 2023年 11卷 24696-24711页

作者： Cui, Enfang Li, Tianzheng Wei, Qian China Telecom Res Inst Beijing Peoples R China

RISC-V is an open-source and royalty-free instruction set architecture (ISA), which opens up a new era of processor innovation. RISC-V has the characteristics of modularization and extensibility, and explicitly supports domain-specific custom extensions. Nowadays, RISC-V is a popular ISA for embedded processors. However, there is still a gap between the capabilities of RISC-V and the requirements of various emerging computing scenarios (e.g., artificial intelligence, cloud computing). Recently, the RISC-V standards organization has continuously introduced new ISA extensions to meet the needs of advanced computing. There are also a variety of novel research proposed customized extensions of RISC-V for certain scenarios. As far as we know, there is a lack of a survey to systematically present the research progress of RISC-V ISA extensions. The goal of this paper is to provide a comprehensive survey on existing works about RISC-V ISA extensions. First, the application scenarios of RISC-V are introduced, and the requirements for ISA extensions are analyzed. Then, we survey the progress of official RISC-V ISA extension specification and recent research on RISC-V ISA extension. Finally, we highlight some possible future research opportunities on the RISC-V ISA extension.

关键词： instruction sets Microprocessors Computer architecture Task analysis Graphics processing units Cloud computing Artificial intelligence RISC-V instruction set architecture extensions survey

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Enhancing a Near-Term Quantum Accelerator's instruction set architecture for Materials Science Applications

IEEE TRANSACTIONS ON QUANTUM ENGINEERING

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IEEE TRANSACTIONS ON QUANTUM ENGINEERING 2020年 1卷

作者： Zou, Xiang Premaratne, Shavindra P. Rol, M. Adriaan Johri, Sonika Ostroukh, Viacheslav Michalak, David J. Caudillo, Roman Clarke, James S. Dicarlo, Leonardo Matsuura, A. Y. Intel Corp Intel Labs Hillsboro OR 97124 USA Intel Corp Components Res Hillsboro OR 97124 USA Delft Univ Technol QuTech NL-2600 GA Delft Netherlands

Quantum computers with tens to hundreds of noisy qubits are being developed today. To be useful for real-world applications, we believe that these near-term systems cannot simply be scaled-down non-error-corrected versions of future fault-tolerant large-scale quantum computers. These near-term systems require specific architecture and design attributes to realize their full potential. To efficiently execute an algorithm, the quantum coprocessor must be designed to scale with respect to qubit number and to maximize useful computation within the qubits' decoherence bounds. In this work, we employ an application-system-qubit co-design methodology to architect a near-term quantum coprocessor. To support algorithms from the real-world application area of simulating the quantum dynamics of a material system, we design a (parameterized) arbitrary single-qubit rotation instruction and a two-qubit entangling controlled-Z instruction. We introduce dynamic gate set and paging mechanisms to implement the instructions. To evaluate the functionality and performance of these two instructions, we implement a two-qubit version of an algorithm to study a disorder-induced metal-insulator transition and run 60 random instances of it, each of which realizes one disorder configuration and contains 40 two-qubit instructions (or gates) and 104 single-qubit instructions. We observe the expected quantum dynamics of the time-evolution of this system.

关键词： Computer architecture microarchitecture quantum algorithm quantum circuit quantum computing quantum gate systems architecture computers and information processing instruction set architecture

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Clockhands: Rename-free instruction set architecture for Out-of-order Processors 23

Clockhands: Rename-free Instruction Set Architecture for Out...

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56th IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Koizumi, Toru Shioya, Ryota Sugita, Shu Amano, Taichi Degawa, Yuya Kadomoto, Junichiro Irie, Hidetsugu Sakai, Shuichi Nagoya Inst Technol Nagoya Aichi Japan Univ Tokyo Tokyo Japan

ISBN: (纸本)9798400703294

Out-of-order superscalar processors are currently the only architecture that speeds up irregular programs, but they suffer from poor power efficiency. To tackle this issue, we focused on how to specify register operands. Specifying operands by register names, as conventional RISC does, requires register renaming, resulting in poor power efficiency and preventing an increase in the front-end width. In contrast, a recently proposed architecture called STRAIGHT specifies operands by inter-instruction distance, thereby eliminating register renaming. However, STRAIGHT has strong constraints on instruction placement, which generally results in a large increase in the number of instructions. We propose Clockhands, a novel instruction set architecture that has multiple register groups and specifies a value as "the value written in this register group.. times before." Clockhands does not require register renaming as in STRAIGHT. In contrast, Clockhands has much looser constraints on instruction placement than STRAIGHT, allowing programs to be written with almost the same number of instructions as Conventional RISC. We implemented a cycle-accurate simulator, FPGA implementation, and first-step compiler for Clockhands and evaluated benchmarks including SPEC CPU. On a machine with an eight-fetch width, the evaluation results showed that Clockhands consumes 7.4% less energy than RISC while having performance comparable to RISC. This energy reduction increases significantly to 24.4% when simulating a futuristic up-scaled processor with a 16-fetch width, which shows that Clockhands enables a wider front-end.

关键词： instruction set architecture Superscalar processor Out-of-order execution Register renaming Compiler Power efficiency Register lifetime

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Flexible instruction set architecture for Programmable Look-up Table based Processing-in-Memory 39

Flexible Instruction Set Architecture for Programmable Look-...

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39th IEEE International Conference on Computer Design ICCD)

作者： Connolly, Mark Sutradhar, Purab Ranjan Indovina, Mark Ganguly, Amlan Rochester Inst Technol Dept Comp Engn Rochester NY 14623 USA

ISBN: (纸本)9781665432191

Processing in Memory (PIM) is a recent novel computing paradigm that is still in its nascent stage of development. Therefore, there has been an observable lack of standardized and modular instruction set architectures (ISA) for the PIM devices. In this work, we present the design of an ISA which is primarily aimed at a recent programmable Look-up Table (LUT) based PIM architecture. Our ISA performs the three major tasks of i) controlling the flow of data between the memory and the PIM units, ii) reprogramming the LUTs to perform various operations required for a particular application, and iii) executing sequential steps of operation within the PIM device. A microcoded architecture of the Controller/Sequencer unit ensures minimum circuit overhead as well as offers programmability to support any custom operation. We provide a case study of CNN inferences, large matrix multiplications, and bitwise computations on the PIM architecture equipped with our ISA and present performance evaluations based on this setup. We also compare the performances with several other PIM architectures.

关键词： instruction set architecture microcode processing in memory look-up table convolutional neural network deep neural network DRAM

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Block-Aware instruction set architecture

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ACM Transactions on architecture and Code Optimization 2006年第3期3卷 327-357页

作者： Zmily, Ahmad Kozyrakis, Christos Stanford University Electrical Engineering Department Palo Alto CA 94305 United States

instruction delivery is a critical component for wide-issue, high-frequency processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and bandwidth are limited by instruction-cache misses, multicycle instruction-cache accesses, and target or direction mispredictions for control-flow operations. This paper presents a block-aware instruction set (BLISS) that allows software to assist with front-end challenges. BLISS defines basic block descriptors that are stored separately from the actual instructions in a program. We show that BLISS allows for a decoupled front-end that tolerates instruction-cache latency, facilitates instruction prefetching, and leads to higher prediction accuracy. © 2006, ACM. All rights reserved.

关键词： Basic block Branch prediction Decoupled architecture instruction fetch instruction set architecture Software hints

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