We present a low power, dual-function encode/decode circuit for a class of reversible low-density parity-check codes. The circuit offers a small silicon footprint, by operating as an analog decoder and reusing resourc...
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We present a low power, dual-function encode/decode circuit for a class of reversible low-density parity-check codes. The circuit offers a small silicon footprint, by operating as an analog decoder and reusing resources to switch into a digital encode mode. In order to achieve this behaviour from a single circuit we have developed mode-switching gates. These logic gates are able to switch between analog (soft) and digital (hard) computation. Only a small overhead in circuit area is required to transform the analog decoder into a full codec. The encode operation can be performed two orders of magnitude faster than the decode operation, making the circuit suitable for full-duplex applications. The low power and small area of the circuit make it an attractive option for battery powered wireless devices. Circuit simulations indicate a decoding latency of 10 mu s with negligible SNR loss with respect to digital sum-product decoders. (C) 2008 Elsevier B.V. All rights reserved.
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