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8th International Conference on Aspect-Oriented Software Development

作者： Villazon, Alex Binder, Walter Moret, Philippe Univ Lugano Fac Informat Lugano Switzerland

ISBN: (纸本)9781605584423

Aspect-oriented programming (AOP) eases the development of profilers, debuggers, and reverse engineering tools. Such tools frequently rely on calling context information. However, current AOP technology, such as AspectJ, does not offer dedicated support for accessing complete calling context within aspects. In this paper, we introduce a novel approach to calling context reification that reconciles flexibility, efficiency, accuracy, and portability. It relies on a generic bytecode instrumentation framework ensuring complete bytecode coverage, including the standard java class library. We compose our program transformations for calling context reification with the AspectJ weaver, providing the aspect developer an efficient mechanism to manipulate a customizable representation of the complete calling context. To highlight the benefits of our approach, we present ReCrash as an aspect using a stack-based calling context representation;ReCrash is an existing tool that generates unit tests to reproduce program failures. In comparison with the original ReCrash tool, our aspect resolves several limitations, is extensible, covers also the standard java class library, and causes less overhead.

关键词： Calling context reification aspect weaving bytecode instrumentation composition of program transformations debugging java virtual machine

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Space-and-Time Efficient Garbage Collectors for Parallel Systems 09

Space-and-Time Efficient Garbage Collectors for Parallel Sys...

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6th ACM International Conference on Computing Frontiers and Workshops

作者： Liu, Shaoshan Wang, Ligang Li, Xiao-Feng Gaudiot, Jean-Luc Univ Calif Irvine Irvine CA 92717 USA

ISBN: (纸本)9781605584133

As multithreaded server applications and runtime systems prevail. garbage collection is becoming ail essential feature to support high performance systems. The fundamental issue of garbage collector (GC) design is to maximize the recycled space with minimal time overhead. This paper proposes two innovative solutions: one to improve space efficiency, and the other to improve time efficiency. To achieve space efficiency, we propose the Space Tuner that utilizes the novel concept of allocation speed to reduce wasted space. Conventional static space partitioning techniques often lead to inefficient space utilization. The Space Tuner adjusts the heap partitioning dynamically such that when a collection is triggered, all space partitions are fully filled. To achieve time efficiency, we propose a novel parallelization method that reduces the compacting GC parallelization problem into a tree traversal parallelization problem. This method can be applied for both normal and large object compaction. Object compaction is hard to parallelize due to strong data dependencies such that the source object can not be moved to its target location until the object originally in the target location has been moved out. Our proposed algorithm overcomes the difficulties by dividing the heap into equal-sized blocks and parallelizing the movement of the independent blocks. It is noteworthy that these proposed algorithms are generic such that they can be utilized in different GC designs.

关键词： Garbage collection java virtual machine

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A Preliminary Workload Analysis of SPECjvm2008

A Preliminary Workload Analysis of SPECjvm2008

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International Conference on Computer Engineering and Technology

作者： Oi, Hitoshi Univ Aizu Aizu Wakamatsu Fukushima Japan

ISBN: (纸本)9780769535210

SPEQvm2008 is a new benchmark program suite for measuring client-side java runtime environment. It replaces JVM98, which has been used for the same purpose for more than ten years. It consists of 38 benchmark programs grouped into eleven categories and has wide variety of workloads from computation-intensive kernels to XML file processors. In this paper, we present the results of running SPECjvm2008 on three machines that have CPUs with the same microarchitecture and different cache sizes and clock speeds. The result of measurements include instruction and data cache reference and miss rates, and the effect of the multi-threading. We relate these workload parameters to the SPECjvm2008 performance metrics. Roughly speaking, an L2 cache of IMB sufficiently lows the cache miss rates of SPECjvm2008 and compared to the single-core, 1.5 to 2 times speed-ups are achieved by dual-core executions.

关键词： java virtual machine Workload Analysis SPECjvm2008

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Laminar: Practical Fine-Grained Decentralized Information Flow Control 09

Laminar: Practical Fine-Grained Decentralized Information Fl...

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ACM SIGPLAN Conference on Programming Language Design and Implementation

作者： Roy, Indrajit Porter, Donald E. Bond, Michael D. McKinley, Kathryn S. Witchel, Emmett Univ Texas Austin Dept Comp Sci Austin TX 78712 USA

ISBN: (纸本)9781605583921

Decentralized information flow control (DIFC) is a promising model for writing programs with powerful, end-to-end security guarantees. Current DIFC systems that run on commodity hardware can be broadly categorized into two types: language-level and operating system-level DIFC. Language level solutions provide no guarantees against security violations on system resources, like files and sockets. Operating system solutions can mediate accesses to system resources, but are inefficient at monitoring the flow of information through fine-grained program data structures. This paper describes Laminar, the first system to implement decentralized information flow control using a single set of abstractions for OS resources and heap-allocated objects. Programmers express security policies by labeling data with secrecy and integrity labels, and then access the labeled data in lexically scoped security regions. Laminar enforces the security policies specified by the labels at runtime. Laminar is implemented using a modified java virtual machine and a new Linux security module. This paper shows that security regions ease incremental deployment and limit dynamic security checks, allowing us to retrofit DIFC policies on four application case studies. Replacing the applications' ad-hoe security policies changes less than 10% of the code, and incurs performance overheads from 1% to 56%. Whereas prior DIFC systems only support limited types of multithreaded programs, Laminar supports a more general class of multithreaded DIFC programs that can access heterogeneously labeled data.

关键词： Information flow control java virtual machine operating systems security region

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Exploiting Multi-Core Processors to Improve Time Predictability for Real-time java Computing

Exploiting Multi-Core Processors to Improve Time Predictabil...

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15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications

作者： Sun, Yu Zhang, Wei So Illinois Univ Dept Elect & Comp Engn Carbondale IL 62901 USA

ISBN: (纸本)9780769537870

As a successful programming language, java has extended its application from general-purpose systems to embedded, real-time systems. However, some of java's excellent features, like automatic memory management and dynamic compilation, bring indeterminism to the execution time of real-time java programs. In this paper, we propose several multi-core approaches to remove or at least reduce the unpredictability inside of java virtual machine (JVM). Our goal is to retain high performance competitive to dynamic compilation and, at the same time, obtain better time predictability for JVM. Also, we study pre-compilation techniques to utilize second core more efficiently. Furthermore, we develop Pre-optimization on Another Core (PoAC) scheme to replace the Adaptive Optimization System (AOS) in jikes JVM, which is very sensitive to execution time variation and impacts time predictability greatly. The experimental results indicate that our approaches are able to reach high performance while greatly reduce execution time variation of java applications.

关键词： Time predictability java virtual machine multicore processors adaptive optimizations

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Applying Dynamic Software Updates to Computationally-Intensive Applications

Applying Dynamic Software Updates to Computationally-Intensi...

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作者： Kim, Dong Kwan Virginia Polytechnic Institute and State University

学位级别：Ph.D.

Dynamic software updates change the code of a computer program while it runs, thus saving the programmer's time and using computing resources more productively. This dissertation establishes the value of and recommends practices for applying dynamic software updates to computationally-intensive applications—a computing domain characterized by long-running computations, expensive computing resources, and a tedious deployment process. This dissertation argues that updating computationally-intensive applications dynamically can reduce their time-to-discovery metrics—the total time it takes from posing a problem to arriving at a solution—and, as such, should become an intrinsic part of their software lifecycle. To support this claim, this dissertation presents the following technical contributions: (1) a distributed consistency algorithm for synchronizing dynamic software updates in a parallel HPC application, (2) an implementation of the Proxy design pattern that is more efficient than the existing implementations, and (3) a dynamic update approach for java virtual machine (JVM)-based applications using the Proxy pattern to offer flexibility and efficiency advantages, making it suitable for computationally-intensive applications. The contributions of this dissertation are validated through performance benchmarks and case studies involving computationally-intensive applications from the bioinformatics and molecular dynamics simulation domains.

关键词： Dynamic Software Updates Computationally-Intensive Applications HPC Binary Rewriting java virtual machine Proxy Pattern

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Lightweight monitors for the java virtual machine

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SOFTWARE-PRACTICE & EXPERIENCE 2005年第3期35卷 281-299页

作者： Yang, BS Moon, SM Ebcioglu, K Seoul Natl Univ Sch Elect Engn Seoul 151742 South Korea IBM Corp TJ Watson Res Ctr Yorktown Hts NY 10598 USA

java supports the monitor construct for language-level synchronization in the context of multithreading. This paper introduces the lightweight monitor, an efficient user-level monitor implementation. The lightweight monitor is useful for single-threaded java programs as well as for multi-threaded java programs with little lock contention. A 32-bit lock is embedded in each object for efficient lock access while other monitor data structures are managed using a hash table. We highly optimized the lock manipulation code, which is translated and inlined by a just-in-time (JIT) compiler. In the most probable cases, only nine SPARC instructions are spent for lock acquisition and five instructions are spent for lock release. Our experimental results indicate that the lightweight monitor is faster than the monitor implementation in the SUN JDK 1.2 RC1 by up to 21 times in the absence of lock contention and by up to seven times in the presence of lock contention. Copyright (C) 2004 John Wiley Sons, Ltd.

关键词： monitor lock java virtual machine just-in-time compilation

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An instruction folding solution for a java processor

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COMPUTER SYSTEMS SCIENCE AND ENGINEERING 2009年第3期24卷 133-143页

作者： Tan Yiyu Yau Chihang Fong, Anthony S. Yang Xiaojian Nanjing Univ Technol Coll Informat Sci & Engn Nanjing 210009 Peoples R China City Univ Hong Kong Dept Elect Engn Kowloon Tong Hong Kong Peoples R China

java is widely applied into embedded devices and network applications. java programs are compiled into java bytecodes, which are executed in the java virtual machine. The java virtual machine is a stack machine and instruction folding is a technique to reduce the redundant stack operations. In this paper, a simple instruction folding algorithm is proposed for a java processor named jHISC, where bytecodes are classified into five categories and the operation results of incomplete folding groups are held for further folding. In the benchmark JVM98, with respect to all stack operations, the percentage of the eliminated P and C type instructions varies from 87% to 98% and the average is about 93%. The reduced instructions are between 37% and 50% of all Operations and the average is 44%.

关键词： Instruction folding java processor java virtual machine bytecode

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Improving java virtual machine reliability for memory-constrained embedded systems.

Improving Java virtual machine reliability for memory-constr...

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42nd Design Automation Conference

作者： Chen, GY Kandemir, M Penn State Univ Dept Comp Sci & Engn University Pk PA 16802 USA

ISBN: (纸本)1595930582

Dual-execution/checkpointing based transient error tolerance techniques have been widely used in the high-end mission critical systems. These techniques, however, are not very attractive for cost-sensitive embedded systems because they require extra resources (e.g., large memory, special hardware, etc), and thus increase overall cost of the system. In this paper, we propose a transient error tolerant java virtual machine (JVM) implementation for embedded systems. Our JVM uses dual-execution and checkpointing to detect and recover from transient errors. However, our technique does not require any special hardware support (except for the memory page protection mechanism, which is commonly available in modern embedded processors), and the memory space overhead it incurs is not excessive. Therefore, it is suitable for memory-constrained embedded systems. We implemented our approach and performed experiments with seven embedded java applications.

关键词： java virtual machine dual execution transient error

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Dedicated hardware based enhancements for implementing the java virtual machine

Dedicated hardware based enhancements for implementing the J...

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International Conference on Embedded Systems and Applications (ESA 05)

作者： Desai, A Cain, G Singh, J Veljanovski, R Victoria Univ Technol Ctr Telecommun & Microelect Melbourne Vic Australia

ISBN: (纸本)193241553X

In spite of the popularly of java, its slow performance and unpredictable execution characteristics are still some of the most challenging issues faced by designers for real-time applications. In the past, numerous architectural enhancements have been investigated to enhance performance and increase predictability. In this paper, dedicated hardware based enhancements that can complement existing design solutions are presented. To achieve high-performance while maintaining simplicity of design, a nested state controller is used for modelling java instructions. This approach enables ahead of synthesis resource sharing and simplified reuse of functional elements. A hardware based automatic memory management sub-system is also presented that provides virtual pointer based memory access for memory allocations. Along with fixed cycle allocation and fast automatic resizing of memory, the memory controller provides predictable management functions. The paper describes a simple system targeted to the Virtex II Pro FPGA.

关键词： java virtual machine real-time java memory management nested state machines

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