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Supporting object accesses in a java processor

IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 2000年第6期147卷 435-443页

作者： Vijaykrishnan, N Ranganathan, N Penn State Univ Dept Comp Sci & Engn University Pk PA 16802 USA Univ S Florida Dept Comp Sci & Engn Tampa FL 33620 USA

Due to java's object-based nature and support for garbage collection, efficient object manipulation and relocation are critical to the execution speed of java code. java Virtual Machine implementations that utilise handle representation such as Sun's java Development Kit 1.1 enable efficient object relocation at the cost of an additional indirection for each object access. The direct address object representations such as those used in CACAO and NET compiler eliminate the indirection overhead, but update during object relocation is complex. A virtual address object cache that reduces the indirection overhead while maintaining the efficiency of object relocation is proposed. The objects in the virtual address cache are addressed directly using the object reference and field offset pair. This eliminates the indirection overhead and off-set addition overhead associated with the handle representation model. A hardware object table that maintains the handles is used to obtain the actual object location on a virtual address cache miss. The performance of the virtual address cache is analysed using various java programs, and is found to reduce 1.5 cycles per object access on an average as compared to the handle representation model for the various benchmarks studied.

关键词： object accesses direct address object representations Compilers, interpreters and other processors program processors object-based nature object-oriented programming virtual address object cache object relocation java code hardware object table File organisation storage management garbage collection Object-oriented programming object reference java java processor

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A java processor architecture for embedded real-time systems

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JOURNAL OF SYSTEMS ARCHITECTURE 2008年第1-2期54卷 265-286页

作者： Schoeberl, Martin Vienna Univ Technol Inst Comp Engn Vienna Austria

Architectural advancements in modern processor designs increase average performance with features such as pipelines, caches, branch prediction, and out-of-order execution. However, these features complicate worst-case execution time analysis and lead to very conservative estimates. JOP (java Optimized processor) tackles this problem from the architectural perspective - by introducing a processor architecture in which simpler and more accurate WCET analysis is more important than average case performance. This paper presents a java processor designed for time-predictable execution of real-time tasks. JOP is the implementation of the java virtual machine in hardware. JOP is intended for applications in embedded real-time systems and the primary implementation technology is in a field programmable gate array. This paper demonstrates that a hardware implementation of the java virtual machine results in a small design for resource-constrained devices. (C) 2007 Elsevier B.V. All rights reserved.

关键词： real-time system time-predictable architecture java processor

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Worst-case execution time analysis for a java processor

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SOFTWARE-PRACTICE & EXPERIENCE 2010年第6期40卷 507-542页

作者： Schoeberl, Martin Puffitsch, Wolfgang Pedersen, Rasmus Ulslev Huber, Benedikt Vienna Univ Technol Inst Comp Engn Vienna Austria Copenhagen Business Sch Dept Informat Copenhagen Denmark

In this paper, we propose a solution for a worst-case execution time (WCET) analyzable java system: a combination of a time-predictable java processor and a tool that performs WCET analysis at java bytecode level. We present a java processor, called JOP, designed for time-predictable execution of real-time tasks. The execution time of bytecodes, the instructions of the java virtual machine, is known to cycle accuracy for JOP. Therefore, JOP simplifies the low-level WCET analysis. A method cache, which fills whole java methods into the cache, simplifies cache analysis. The WCET analysis tool is based on integer linear programming. The tool performs the low-level analysis at the bytecode level and integrates the method cache analysis. An integrated data-flow analysis performs receiver-type analysis for dynamic method dispatches and loop-bound analysis. Furthermore, a model checking approach to WCET analysis is presented where the method cache can be exactly simulated. The combination of the time-predictable java processor and the WCET analysis tool is evaluated with standard WCET benchmarks and three real-time applications. The WCET friendly architecture of JOP and the integrated method cache analysis yield tight WCET bounds. Comparing the exact, but expensive, model checking-based analysis of the method cache with the static approach demonstrates that the static approximation of the method cache is sufficiently tight for practical purposes. Copyright (C) 2010 John Wiley & Sons, Ltd.

关键词： worst-case execution time java processor real-time system

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Enhancing java processor performance with smart dynamic folding

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JOURNAL OF THE CHINESE INSTITUTE OF ENGINEERS 2000年第6期23卷 711-719页

作者： Chang, LC Ton, LR Kao, MF Chung, CP Natl Chiao Tung Univ Dept Comp Sci & Informat Engn Hsinchu 300 Taiwan Ind Technol Res Inst Comp & Commun Res Labs Hsinchu 310 Taiwan

The java processor is suitable for Internet appliances or embedded controllers due to its speed and low memory requirement. However, its performance is severely limited by true data dependence. In this work, we present a smart and dynamic stack operations folding - POC model-based folding. The stack instructions are classified into P,O, and C three types. The folding algorithm can automatically determine the folding relations among all the instructions based on the type and folding attributes of each instruction. The proposed algorithm has no requirement to match different patterns. A typical folding mechanism design based on this model is then introduced. Also, the performance of various folding methods based on the POC model is evaluated. Simulation data indicate that the 4-foldable method eliminates 84% of all stack operations. Furthermore, the 2-, 3-, and 4-foldable methods accelerate the overall program by 1.22, 1.32 and 1.34, respectively, as compared to a java processor without folding.

关键词： stack machine stack operations folding true data dependence java processor

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A java processor with hardware-support object-oriented instructions

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MICROprocessorS AND MICROSYSTEMS 2006年第8期30卷 469-479页

作者： Tan, Yiyu Yiu, Lo Wan Hang, Yau Chi Li, Richard Fong, Anthony S. City Univ Hong Kong Dept Elect Engn Hong Kong Hong Kong Peoples R China

java is widely applied from the small embedded devices to enterprise systems nowadays due to its object-oriented features and corresponding advantages of security, robustness, and platform independence. java programs are compiled into java Bytecodes, which are executed in the java virtual machine. Among the current hardware or software solutions to the java virtual machine, the object-oriented related Bytecodes are implemented by software traps or microcode, and their performance does not match well with the essential requirements of memory-constraint embedded devices, such as real-time operations and low power consumptions. In this paper, a novel java processor named jHISC is proposed, which mainly targets java applications in the small embedded devices. In jHISC, 94% of Bytecodes and 83% of the object-oriented related Bytecodes are implemented by hardware directly. Compared with Picojava II and JOP, jHISC speeds up the overall performance about 30% and 183%, respectively. (C) 2006 Elsevier B.V. All rights reserved.

关键词： java processor Bytecode object-oriented programming operand descriptor

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AUTOMATIC MEMORY MANAGEMENT FOR EMBEDDED REAL-TIME java processor JPOR-32

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INTELLIGENT AUTOMATION AND SOFT COMPUTING 2011年第8期17卷 1193-1205页

作者： Hu, Guang Chai, Zhilei Tu, Shiliang Fudan Univ Sch Comp Sci Shanghai 200433 Peoples R China Shanghai Int Studies Univ Dept Comp Sci Shanghai 200083 Peoples R China Jiangnan Univ Sch Informat Technol Wuxi 214122 Peoples R China

Currently, java has been gradually applied in embedded real-time areas like robotics, control system, etc. owning to its advantages like robustness, security, etc. In order to improve the performance of java's execution engine for embedded real-time applications, JPOR-32, an embedded real-time java processor, is designed. Based on it, this paper presents the automatic memory management (AMM) mechanism for embedded real-time java processor. JPOR-32 provides architectural support as well as instruction level support for AMM. Its preprocessing mechanism reduces the complexity of the implementation of AMM, enhances the run-time efficiency, and promotes predictability of the worst-case execution time. The system design of JPOR-32 makes AMM of class area avoided, and the optimized design of instruction set provides effective support for space checking and garbage collection scheduling. This paper also proposes an object reference format which provides supports for objects tracing, heap scanning, synchronization, etc., and lays the foundation for the implementation of suitable garbage collection algorithm. Moreover, this paper gives the analysis of the feature of runtime environment of embedded java processor, and implements a suitable improved generational garbage collector.

关键词： memory management garbage collector java processor real-time java embedded system intelligent automation

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Towards the Formal Verification of a java processor in Event-B

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ELECTRONIC NOTES IN THEORETICAL COMPUTER SCIENCE 2008年第C期201卷 45-67页

作者： Evans, Neil Grant, Neil AWE Aldermaston England

Formal verification is becoming more and more important in the production of high integrity microprocessors. The general purpose formal method called Event-B is the latest incarnation of the B Method: it is a proof-based approach with a formal notation and refinement technique for modelling and verifying systems. Refinement enables implementation-level features to be proven correct with respect to an abstract specification of the system. In this paper we demonstrate an initial attempt to model and verify Sandia National Laboratories' Score processor using Event-B. The processor is an (almost complete) implementation of a java Virtual Machine in hardware. Thus, refinement-based verification of the Score processor begins with a formal specification of java bytecode. Traditionally, B has been directed at the formal development of software systems. The use of B in hardware verification could provide a means of developing combined software/hardware systems, i.e. codesign.

关键词： java processor microcoded architecture Event-B refinement

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Stack Memory Design for a Low-cost Instruction Folding java processor

Stack Memory Design for a Low-cost Instruction Folding Java ...

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IEEE International Symposium on Circuits and Systems

作者： Lin, Zi-Gang Kuo, Han-Wen Guo, Zi-Jing Tsai, Chun-Jen Natl Chiao Tung Univ Dept Comp Sci Hsinchu Taiwan

ISBN: (纸本)9781467302197

In this paper, we propose the design of the stack memory for a low-cost java processor that explores instruction-level parallelism. The java virtual machine (JVM) is a stack machine where the instruction execution pipeline uses a stack to store intermediate computation results and local variables. High performance java processors often use a large stack cache to enable parallel accesses to operands and local variables to achieve instruction-level parallelism. We propose a low-cost alternative of stack memory design that allows the java processor to access the critical stack operands and local variables concurrently. The stack memory is constructed using seven registers and two blocks of dual-port on-chip SRAM;and is optimized for the java instruction set architecture. When coupled with a low-cost two-way instruction folding pipeline, micro-benchmark results show that the proposed architecture can achieve up to 45.4% 2-fold instruction folding rate.

关键词： java processor INSTRUCTION-LEVEL PARALLELISM STACK MEMORY DESIGN EMBEDDED SYSTEMS

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An Evaluation of Safety-Critical java on a java processor 17

An Evaluation of Safety-Critical Java on a Java Processor

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17th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC)

作者： Rios, Juan Ricardo Schoeberl, Martin Tech Univ Denmark Dept Appl Math & Comp Sci Odense Denmark

ISBN: (纸本)9781479944309

The safety-critical java (SCJ) specification provides a restricted set of the java language intended for applications that require certification. In order to test the specification, implementations are emerging and the need to evaluate those implementations in a systematic way is becoming important. In this paper we evaluate our SCJ implementation which is based on the java Optimized processor JOP and we measure different performance and timeliness criteria relevant to hard real-time systems. Our implementation targets Level 0 and Level 1 of the specification and to test it we use a series of micro benchmarks, an application-based benchmark, and a reduced set of a SCJ technology compatibility kit. We evaluate the accuracy of periods, linear-time memory allocation, aperiodic event handling, dispatch latency for interrupts, context switch preemption latency, and synchronization.

关键词： Real-time systems Embedded systems java Safety-critical systems Safety-critical java java processor

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Design of Instruction Execution Stage for an Embedded Real-Time java processor

Design of Instruction Execution Stage for an Embedded Real-T...

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International Conference on Intelligent Computing and Information Science

作者： Hu, Guang Chai, Zhilei Zhao, Wenke Shanghai Int Studies Univ Dept Comp Sci Shanghai 200086 Peoples R China Fudan Univ Sch Comp Sci Shanghai 200433 Peoples R China Jiangnan Univ Sch Internet Things Wuxi 214122 Peoples R China Intel Corp Intel Asia Pacific Res & Dev Ltd Shanghai 200241 Peoples R China

ISBN: (纸本)9783642181337

Now, as a popular language for the development of sever and desktop applications, java is also playing a more and more important role in embedded development owning to its features like platform independence, high development efficiency, etc. Accordingly, JPOR-32, a 32-bit java processor optimized for real-time specification for java, is designed. In this paper, taking JPOR-32 as an example, the instruction execution stage design for embedded real-time java processor is presented. The run time operand stack and method stack is implemented, which lays the foundations of execution of instruction set based on stack. For instruction execution stage, this paper presents on emphasis the control signal operation mechanism and the instruction execution stage data path.

关键词： java processor real-time java instruction execution real-time system

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