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4th International Conference on ASIC

作者： Zhang, JJ Li, FH Ge, YQ Yue, ZW Yang, ZL Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China

ISBN: (纸本)0780366778

Starting from the java Card Virtual Machine (JCVM) specification and the picojava-II architecture, a pipelined java card processor has been designed. It implements all of JCVM bytecodes with 16-bit operands in three different ways according to the complexity of their functions. It utilizes a one-read one-write dual-port RAM as java stack in order to reduce the consumption of limited memory footprint on a smart card. It also includes a Smart Card extension instruction set, which is used to support the low-level hardware operations required by Smart Card Operating System (SCOS). An assembler for this processor is developed, and a simple SCOS with 10 APDU commands is written. The SCOS is simulated in a simulation environment based on the HDL model of this processor. Then the processor with an ISO standard serial I/O port is implemented and verified on a hardware verification system based on FPGA. The results of real interactions with card reader show that this processor can meet the requirements of smart card applications.

关键词： java microprocessor chips smart cards pipeline processing instruction sets virtual machines java processor smart card java Card Virtual Machine picojava-II architecture pipelined architecture Smart Card extension instruction set RAM APDU command Smart Card Operating System assembler HDL model FPGA hardware verification system 16 bit

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Memory Access Mechanism in Embedded Real-Time java processor

Memory Access Mechanism in Embedded Real-Time Java Processor

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2nd International Conference on Computer and Automation Engineering (ICCAE)

作者： Hu, Guang Chai, Zhilei Tu, Shiliang Fudan Univ Dept Comp Sci & Engn Shanghai Peoples R China Shanghai Int Studies Univ Dept Comp Sci Shanghai Peoples R China Jiangnan Univ Sch Informat Technol Ctr Intelligent & High Performance Comp Wuxi Peoples R China

ISBN: (纸本)9781424455690

Currently, java has been gradually applied in such areas as robotics, industrial control, and other embedded real-time applications owning to its advantages like platform independence, robustness, security, etc. In order to improve the performance of java's execution engine for embedded real-time applications, an embedded real-time java processor JPOR-32 (32-bit java processor Optimized for RTSJ) is designed. In this paper, the memory access mechanism of JPOR-32 is presented. In JPOR-32, the optimized memory organization structure is designed to implement the runtime data areas of the java virtual machine (JVM). Based on it, with the preprocessing operation, the memory access instructions optimization is implemented as well. The preprocessing operation enables the JVM's runtime operations involving dynamic loading, verification, preparation, resolution, etc. to be handled in advance. It not only provides an efficient and convenient way to implement memory access, but also makes the contribution to the WCET predictability. As to the memory management, in accordance with the Real-Time Specification for java (RTSJ), garbage collection (GC) is not allowed in the immortal memory as well as the scoped memory, and in the heap, JPOR-32 adopts improved GC scheme suitable for embedded real-time java environment. Besides, with the architectural support of the pipelined datapath, JPOR-32 provides effective supports for efficient and predictable memory access.

关键词： memory access java processor embeeded real-time java

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Temporal Multithreading Architecture Design for a java processor

Temporal Multithreading Architecture Design for a Java Proce...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Su, Hung-Cheng Wu, Tsung-Han Tsai, Chun-Jen Natl Chiao Tung Univ Dept Comp Sci Hsinchu Taiwan

ISBN: (纸本)9781479934324

In this paper, we presents the design of a hardware temporal multi-threading architecture for a java processor. The java virtual machine (JVM) model is a stack machine where the process state is the snapshot of the java stack If the runtime stack is stored (or cached) in on-chip memory for performance reasons, the backup and restoration of the java runtime stacks for context switching would be expensive operations. We propose a Ping-Pong buffer architecture in this paper to facilitate fully hardware-based multi-threading capability for a java processor. The proposed hardware architecture has been implemented and verified on an FPGA platform, Xilinx ML605. The experimental results show that the proposed context-switching efficiency is much higher than that of a software-based VM such as the CVM-JIT. Therefore, the proposed hardwired java processor is promising for embedded applications that require heavy multi-threading operations.

关键词： java processor TEMPORAL MULTITHREADING EMBEDDED SYSTEMS

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An effective instruction optimization method for embedded real-time java processor

An effective instruction optimization method for embedded re...

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34th International Conference on Parallel Processing (ICPP)

作者： Chai, ZL Tang, ZQ Wang, LM Tu, SL Fudan Univ Dept Comp Sci & Engn Shanghai 200433 Peoples R China

ISBN: (纸本)0769523811

A method to optimize instructions in embedded real-time java processors is proposed. It can reduce the CPI (Cycles per Instruction) and simplify the implementation of complex instructions, as well as make the WCET (Worst Case Execution Time) of the optimized instructions more predictable. Because this method optimizes instruction itself, it can be used together with other architectural optimization methods such as pipeline or out-of-order execution etc.

关键词： java processor embedded real-time java processor instruction optimization WCET (Worst Case Execution Time)

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An instruction folding solution for a java processor

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COMPUTER SYSTEMS SCIENCE AND ENGINEERING 2009年第3期24卷 133-143页

作者： Tan Yiyu Yau Chihang Fong, Anthony S. Yang Xiaojian Nanjing Univ Technol Coll Informat Sci & Engn Nanjing 210009 Peoples R China City Univ Hong Kong Dept Elect Engn Kowloon Tong Hong Kong Peoples R China

java is widely applied into embedded devices and network applications. java programs are compiled into java bytecodes, which are executed in the java virtual machine. The java virtual machine is a stack machine and instruction folding is a technique to reduce the redundant stack operations. In this paper, a simple instruction folding algorithm is proposed for a java processor named jHISC, where bytecodes are classified into five categories and the operation results of incomplete folding groups are held for further folding. In the benchmark JVM98, with respect to all stack operations, the percentage of the eliminated P and C type instructions varies from 87% to 98% and the average is about 93%. The reduced instructions are between 37% and 50% of all Operations and the average is 44%.

关键词： Instruction folding java processor java virtual machine bytecode

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Exploiting an abstract-machine-based framework in the design of a java ILP processor

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JOURNAL OF SYSTEMS ARCHITECTURE 2009年第1期55卷 53-60页

作者： Wang, H. C. Yuen, C. K. Natl Univ Singapore Dept Comp Sci Sch Comp Singapore 117543 Singapore

Machines bridge the gap between the high-level of programming languages and the low-level mechanisms of a real machine. The paper proposed a general abstract-machine-based framework (AMBF) to build instruction level parallelism processors using the instruction tagging technique. The constructed processor may accept code written in any (abstract or real) machine instruction set, and produce tagged machine code after data conflicts are resolved. This requires the construction of a tagging unit which emulates the sequential execution of the program using tags rather than actual values. The paper presents a java ILP processor by using the proposed framework. The java processor takes advantage of the tagging unit to dynamically translate java bytecode instructions to RISC-like tag-based instructions to facilitate the use of a general-purpose RISC core and enable the exploitation of instruction level parallelism. We detailed the java ILP processor architecture and the design issues. Benchmarking of the java processor using SpecJVM98 and Unpack has shown the overall ILP speedup improvement between 78% and 173%. (c) 2008 Elsevier B.V. All rights reserved.

关键词： Abstract machine java processor Embedded processor ILP VLIW

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A hardware-oriented object model for java in an embedded processor

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MICROprocessorS AND MICROSYSTEMS 2018年 63卷 85-97页

作者： Tan Yiyu RIKEN Ctr Computat Sci Wako Saitama Japan

java has been applied widely because of its versatility, robustness, platform portability, and security. In java, object related instructions dominate the execution speed of applications due to their complexity and time-consuming, and object model determines the implementation of object related instructions because it affects the object access. In this research, an object model is developed to provide parallel access of object fields, eliminate the indirections during object access, and target direct hardware implementation of object manipulation instructions. In the java benchmark JVM98, the jHISC V4, an embedded processor based on the proposed object model for mobile and embedded computing, averagely achieves performance gain by 1.86 times and 0.39 times in the object manipulation operations, and 1.14 times and 0.21 times in all operations over the JOP and jHISC V3, respectively.

关键词： Object model java java processor Operand descriptor

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Temporal Multithreading Architecture Design for a java processor

Temporal Multithreading Architecture Design for a Java Proce...

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IEEE International Symposium on Circuits and Systems

作者： Hung-Cheng Su Tsung-Han Wu Chun-Jen Tsai Department of Computer Science National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)9781479934331

In this paper, we presents the design of a hardware temporal multi-threading architecture for a java processor. The java virtual machine (JVM) model is a stack machine where the process state is the snapshot of the java stack. If the runtime stack is stored (or cached) in on-chip memory for performance reasons, the backup and restoration of the java runtime stacks for context switching would be expensive operations. We propose a Ping-Pong buffer architecture in this paper to facilitate fully hardware-based multi-threading capability for a java processor. The proposed hardware architecture has been implemented and verified on an FPGA platform, Xilinx ML605. The experimental results show that the proposed context-switching efficiency is much higher than that of a software-based VM such as the CVM-JIT. Therefore, the proposed hardwired java processor is promising for embedded applications that require heavy multi-threading operations.

关键词： java processor TEMPORAL MULTITHREADING EMBEDDED SYSTEMS

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An Instruction Reconfigurable Framework for RTSJ-optimized java processor

An Instruction Reconfigurable Framework for RTSJ-optimized J...

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2008年国际电子商务、工程及科学领域的分布式计算和应用学术研讨会

作者： Xiaolong Ren~(1 2) Zhilei Chai~1 1 School of Information Technology,Jiangnan University,Wuxi,Jiangsu 214122,China 2 Department of Continuing Education,Shanxi Architectural Technical College,Taiyuan,Shanxi 030006,China

Due to the preeminent work of the real-time specification for java(RTSJ),java is increasingly expected to become the leading programming language in embedded real-time *** order to provide an efficient real-time java platform suitable for embedded applications,we designed a FPGA-centric java processor optimized for *** the software for most of the embedded systems is application-specific and hardly changed,some bytecodes are probably never used in a special java-based embedded *** this paper,an instruction reconfigurable framework for the java processor is *** on this framework,the processor can be customized according to the application *** the bytecodes really used in the application will be implemented, making the java processor resource-saving and organization simple.

关键词： Real-time Systems Real-time Specification for java java processor Worst Case Execution Time Instruction Reconfigurable

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JAIP-MP: A Four-Core java Application processor 23

JAIP-MP: A Four-Core Java Application Processor

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23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

作者： Tsai, Chun-Jen Wu, Tsung-Han Su, Hung-Cheng Natl Chiao Tung Univ Dept Comp Sci Hsinchu 30050 Taiwan

ISBN: (纸本)9781467391405

In this paper, we present the design of a four-core java application processor, JAIP-MP. Each processor core in JAIP-MP is a hardwired java core that supports dynamic class loading, two-fold bytecode execution, object-oriented dynamic resolution, method and object caching, java exception handling, and temporal multithreading. For JAIP-MP, a global load-balancing task manager is used to evenly distribute java threads among the local task queues of every processor cores. In addition, a data coherence controller is designed to enforce coherence across all data caches and to perform synchronization operations among java threads of all processor cores. Since thread management and synchronization mechanisms are completely implemented in hardware, the single-core multi-tasking performance of JAIP-MP is much higher than that of a software-based VM running on a traditional OS kernel such as Linux. For execution of multithreading applications, the speedup of a four-core JAIP-MP system can be up to 3.69 times faster than a single-core JAIP system, tested using the JemBench parallel benchmark programs.

关键词： java processor multi-core embedded SoC hardwired multi-threading cache coherence

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